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18 IR REMOTE CONTROLLER (REMC3)
REMC3 Data Bit Active Pulse Length Register
Register name
Bit
REMC3APLEN
15–0 APLEN[15:0]
Bits 15–0 APLEN[15:0]
These bits set the active pulse length of the data signal (high period when the REMC3DBCTL.RE-
MOINV bit = 0 or low period when the REMC3DBCTL.REMOINV bit = 1).
The REMO pin output is set to the active level from the 16-bit counter for data signal generation
= 0x0000 and it is inverted to the inactive level when the counter exceeds the REMC3APLEN.
APLEN[15:0] bit-setting value. The data signal duty ratio is determined by this setting and the
REMC3DBLEN.DBLEN[15:0] bit-setting. (See Figure 18.4.3.3.)
Before this register can be rewritten, the REMC3DBCTL.MODEN bit must be set to 1.
REMC3 Data Bit Length Register
Register name
Bit
REMC3DBLEN
15–0 DBLEN[15:0]
Bits 15–0 DBLEN[15:0]
These bits set the data length of the data signal (length of one cycle).
A data signal cycle begins with the 16-bit counter for data signal generation = 0x0000 and ends when
the counter exceeds the REMC3DBLEN.DBLEN[15:0] bit-setting value. (See Figure 18.4.3.3.)
Before this register can be rewritten, the REMC3DBCTL.MODEN bit must be set to 1.
REMC3 Status and Interrupt Flag Register
Register name
Bit
REMC3INTF
15–11 –
10
9
8
7–2 –
1
0
Bits 15–11 Reserved
Bit 10
DBCNTRUN
This bit indicates whether the 16-bit counter for data signal generation is running or not. (See Figure
18.4.4.1.)
1 (R):
Running (Counting)
0 (R):
Idle
Bit 9
DBLENBSY
This bit indicates whether the value written to the REMC3DBLEN.DBLEN[15:0] bits is transferred to
the REMC3DBLEN buffer or not. (See Figure 18.4.4.1.)
1 (R):
Transfer to the REMC3DBLEN buffer has not completed.
0 (R):
Transfer to the REMC3DBLEN buffer has completed.
While this bit is set to 1, writing to the REMC3DBLEN.DBLEN[15:0] bits is ineffective.
Bit 8
APLENBSY
This bit indicates whether the value written to the REMC3APLEN.APLEN[15:0] bits is transferred to
the REMC3APLEN buffer or not. (See Figure 18.4.4.1.)
1 (R):
Transfer to the REMC3APLEN buffer has not completed.
0 (R):
Transfer to the REMC3APLEN buffer has completed.
While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective.
18-10
Bit name
Initial
0x0000
Bit name
Initial
0x0000
Bit name
Initial
0x00
DBCNTRUN
0
DBLENBSY
0
APLENBSY
0
0x00
DBIF
0
APIF
0
Seiko Epson Corporation
Reset
R/W
H0
R/W
Writing enabled when REMC3DBCTL.
MODEN bit = 1.
Reset
R/W
H0
R/W
Writing enabled when REMC3DBCTL.
MODEN bit = 1.
Reset
R/W
–
R
–
H0/S0
R
Cleared by writing 1 to the
REMC3DBCTL.REMCRST bit.
H0
R
Effective when the REMC3DBCTL.
BUFEN bit = 1.
H0
R
–
R
–
H0/S0
R/W
Cleared by writing 1 to this bit or the
REMC3DBCTL.REMCRST bit.
H0/S0
R/W
S1C31D41 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.1)
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