Uart (Uart3) Ch.2 - Epson Arm S1C31 Series Technical Manual

Address Register name
0x0020 UART3_1INTF
060c (UART3 Ch.1 Status
and Interrupt Flag
Register)
0x0020 UART3_1INTE
060e (UART3 Ch.1
Interrupt Enable
Register)
0x0020 UART3_1
0610 TBEDMAEN
(UART3 Ch.1
Transmit Buffer
Empty DMA Request
Enable Register)
0x0020 UART3_1
0612 RB1FDMAEN
(UART3 Ch.1 Receive
Buffer One Byte Full
DMA Request Enable
Register)
0x0020 UART3_1CAWF
0614
(UART3 Ch.1 Carrier
Waveform Register)
0x0020 0620–0x0020 0634
Address Register name
0x0020 UART3_2CLK
0620 (UART3 Ch.2 Clock
Control Register)
0x0020 UART3_2MOD
0622
(UART3 Ch.2 Mode
Register)
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Bit Bit name
15–10 –
9 RBSY
8 TBSY
7 –
6 TENDIF
5 FEIF
4 PEIF
3 OEIF
2 RB2FIF
1 RB1FIF
0 TBEIF
15–8 –
7 –
6 TENDIE
5 FEIE
4 PEIE
3 OEIE
2 RB2FIE
1 RB1FIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RB1FDMAEN[3:0]
15–8 –
7–0 CRPER[7:0]
Bit Bit name
15–9 –
8 DBRUN
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
15–13 –
12 PECAR
11 CAREN
10 BRDIV
9 INVRX
8 INVTX
7 –
6 PUEN
5 OUTMD
4 IRMD
3 CHLN
2 PREN
1 PRMD
0 STPB
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0 H0/S0 R
0 H0/S0 R
0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
0 H0/S0 R
1 H0/S0 R
0x00 – R
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 H0 R/W
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
Remarks
–
Cleared by writing 1.
Cleared by writing 1 or read-
ing the UART3_1RXD register.
Cleared by writing 1.
Cleared by reading the
UART3_1RXD register.
Cleared by writing to the
UART3_1TXD register.
–
–
–
–

UART (UART3) Ch.2

Remarks
–
–
AP-A-33