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DMAC Control Data Base Pointer Register
Register name
Bit
DMACCPTR
31–0 CPTR[31:0]
Bits 31–0 CPTR[31:0]
These bits set the leading address of the data structure.
Depending on the number of channels implemented, low-order bits are configured for read only.
Table 6.8.2 CPTR Writable/Read-Only Bits Depending On Number of Channel Implemented
Number of channel
DMAC Alternate Control Data Base Pointer Register
Register name
Bit
DMACACPTR
31–0 ACPTR[31:0]
Bits 31–0 ACPTR[31:0]
These bits show the alternate data structure base address.
DMAC Software Request Register
Register name
Bit
DMACSWREQ
31–0 SWREQ[31:0]
Bits 31–0 SWREQ [31:0]
These bits issue a software DMA transfer request to each channel.
1 (W):
Issue a software DMA transfer request
0 (W):
Ineffective
Each bit corresponds to a DMAC channel (e.g. bit n corresponds to Ch.n). The high-order bits for the
unimplemented channels are ineffective.
DMAC Request Mask Set Register
Register name
Bit
DMACRMSET
31–0 RMSET[31:0]
Bits 31–0 RMSET[31:0]
These bits mask DMA transfer requests from peripheral circuits.
1 (W):
Mask DMA transfer requests from peripheral circuits
0 (W):
Ineffective
1 (R):
DMA transfer requests from peripheral circuits have been disabled.
0 (R):
DMA transfer requests from peripheral circuits have been enabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name
Initial
0x0000
0000
Writable bits
implemented
1
CPTR[31:5]
2
CPTR[31:6]
3–4
CPTR[31:7]
5–8
CPTR[31:8]
9–16
CPTR[31:9]
17–32
CPTR[31:10]
Bit name
Initial
–
Bit name
Initial
–
Bit name
Initial
0x0000
0000
Seiko Epson Corporation
6 DMA CONTROLLER (DMAC)
Reset
R/W
H0
R/W
–
Read-only bits
CPTR[4:0]
CPTR[5:0]
CPTR[6:0]
CPTR[7:0]
CPTR[8:0]
CPTR[9:0]
Reset
R/W
H0
R
–
Reset
R/W
–
W
–
Reset
R/W
H0
R/W
–
Remarks
Remarks
Remarks
Remarks
6-11
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