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14. Disable the DMA requests to be sent to both the DMA channels using the QSPI_nTBEDMAEN.TBED-
MAENx and QSPI_nRBFDMAEN.RBFDMAENy bits.
15. Set the channel request masks for both the DMA channels using the DMA controller register.
16. Disable both the DMA channels using the DMA controller register.
17. Negate the slave select signal by controlling the QSPI_nCTL.MSTSSO bit or the general-purpose output
port (if necessary).
15.5.6 Data Reception in Memory Mapped Access Mode
A data receiving procedure, and 32-bit and 8/16-bit received data read operations in memory mapped access mode
are shown below. Figures 15.5.6.1 to 15.5.6.7 show their timing charts and a flowchart.
Data receiving procedure
QSPI Flash memories of different manufacturers have a different XIP operation mode setup procedure. The
procedure described below assumes that the external Flash memory has already been placed into XIP operation
mode.
1. Send a read command that supports XIP mode to the external Flash memory.
For the sending procedure, see Steps 1 to 5 of the data sending procedure described in Section 15.5.4, "Data
Transmission in Master Mode." The slave select signal that has been asserted should be left unchanged.
2. Set the QSPI_nMADRH.RMADR[31:20] bits.
3. Write 1 to the QSPI_nMMACFG2.MMAEN bit. (Enable memory mapped access mode)
4. Read the memory mapped access area for external Flash memory with an 8, 16, or 32-bit memory read in-
struction.
This operation directly reads data within the 1M-byte external Flash memory area remapped to the memory
mapped access area for external Flash memory at Step 2.
5. Repeat Step 4 as needed.
When reading an address outside the remapped area, start from Step 2 again after setting the QSPI_nM-
MACFG2.MMAEN bit to 0 once.
Data receiving operations (32-bit read)
In memory mapped access mode, the internal state machine detects the address in the memory mapped access
area from which data is read. If it is the first read operation after the QSPI has entered memory mapped access
mode, the state machine generates an address cycle and a dummy cycle (including the XIP activation confirma-
tion bit(s)). At the same time, it pulls the HREADY signal on the internal system bus down to low.
The address cycle can be configured for 24 or 32-bit addresses and it consists of two transfer cycles. The
state machine determines actual Flash memory address from the memory mapped access area start address,
the read address in that area, and the external Flash memory remapping start address set using the QSPI_
nRMADRH[31:20] bits. The first transfer cycle is an 8-bit transfer that sends the high-order 8 bits of the ad-
dress (when 24-bit address cycle is configured) or a 16-bit transfer that sends the high-order 16 bits of the ad-
dress (when 32-bit address cycle is configured). The second cycle is fixed at 16-bit transfer that sends the low-
order 16 bits of the address.
A dummy cycle follows. The XIP activation confirmation byte set in the QSPI_nMB.XIPACT[7:0] bits is sent
at the beginning of the cycle.
Then, the state machine starts fetching data from the external Flash memory. Once 32-bit data has been fetched
into the internal FIFO, the FIFO read level is incremented (FIFO data ready). At this time, the HREADY signal
reverts to high and the data fetched into the FIFO is sent to the internal system bus. The state machine prefetch-
es two more 32-bit data from the continuous address and stores it into the FIFO.
If the address in the memory mapped access area that is continuous to the previous read address is read when
the FIFO contains the prefetched data (FIFO data ready status), the prefetched data is sent to the internal system
bus with the HREADY signal held high (zero-wait read).
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
15 Quad Synchronous Serial Interface (QSPI)
(Remap external Flash memory)
Seiko Epson Corporation
15-17
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