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22 HW Processor (HWP) and Sound Output (SDAC2)
1) hwp_sleep
After the MCU boots up, the HWP enters this state (HWPCTL.HWPEN bit = 0). In this state, the clock supply
to the HWP stops. By setting the HWPCTL.HWPEN bit to 1 after configuring the Memory Check function reg-
isters as shown in "Initialization" above, the HWP transits to mc_state_init state.
2) mc_state_init
After the HWPCTL.HWPEN bit is set to 1, the HWP enters this state and initializes the internal circuit accord-
ing to the settings of the Memory Check function registers. Upon completion of the initial processing, the HWP
transits to mc_state_idle state.
3) mc_state_idle
This is the state in which the Memory Check function is idle. This state allows issuance of a memory check
command. After a memory check command is issued, the HWP transits to a state from 4) to 7) to start memory
check.
4) mc_state_ram_rw
This is the state in which the HWP is performing the RAM read/write check. When the RAM Check R/W Start
command is issued in mc_state_idle state, the HWP transits to this state. When the check has completed or the
Memory Check Stop command is issued, the HWP returns to mc_state_idle state.
5) mc_state_ram_march_c
This is the state in which the HWP is performing the RAM check using the March-C algorithm. When the
RAM Check March-C Start command is issued in mc_state_idle state, the HWP transits to this state. When the
check has completed or the Memory Check Stop command is issued, the HWP returns to mc_state_idle state.
6) mc_state_checksum
This is the state in which the HWP is performing the Flash memory check that calculates the checksum. When
the Flash Checksum Start command is issued in mc_state_idle state, the HWP transits to this state. When the
check has completed or the Memory Check Stop command is issued, the HWP returns to mc_state_idle state.
7) mc_state_crc
This is the state in which the HWP is performing the Flash memory check that calculates the CRC. When the
Flash CRC Start command is issued in mc_state_idle state, the HWP transits to this state. When the check has
completed or the Memory Check Stop command is issued, the HWP returns to mc_state_idle state.
The current operating state can be monitored by reading the STATE.STATE[15:0] bits (except hwp_sleep). Fur-
thermore, an interrupt can be generated when a state transition to the designated state occurs.
Memory check commands
Table 22.4.2.1 lists the Memory Check function commands.
Command
RAM Check R/W Start
RAM Check March-C Start Start RAM check (March-C)
Flash Checksum Start
Flash CRC Start
Memory Check Stop
The memory check start command can be issued only in mc_state_idle state.
Follow the procedure below to issue a command.
1. Confirm that the STATE.STATE[15:0] bits = 0x0001 (mc_state_idle).
2. Confirm that the STATUS.READY bit = 1.
3. Set the COMMAND.COMMAND[7:0] bits.
4. Set the MEMADDR.ADDRESS[31:0] bits.
5. Set the MEMSIZE.SIZE[31:0] bits.
22-14
Table 22.4.2.1 List of Memory Check Commands
Function
Start RAM check (read/write)
Start Flash check (checksum)
Start Flash check (CRC)
Stop memory check
Seiko Epson Corporation
Issuable state
mc_state_idle
mc_state_idle
mc_state_ram_march_c
mc_state_idle
mc_state_idle
mc_state_ram_rw,
mc_state_ram_march_c,
mc_state_checksum,
mc_state_crc
(Command acceptable)
(Select command)
(Specify check start address)
(Specify check size (byte))
S1C31D41 TECHNICAL MANUAL
Transit destination state
mc_state_ram_rw
mc_state_checksum
mc_state_crc
mc_state_idle
(Rev. 1.1)
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