Dma Transfer Requests; Control Registers; I2C Ch.n Clock Control Register - Epson Arm S1C31 Series Technical Manual

16 I 2 C (I2C)
(2) STOP condition interrupt
Master mode
Slave mode
(f : I2C operating clock frequency [Hz], BRT: I2C_nBR.BRT[6:0] bits setting value (1 to 127))
CLK_I2Cn

16.6 DMA Transfer Requests

The I2C has a function to generate DMA transfer requests from the causes shown in Table 16.6.1.
Cause to request DMA transfer
DMA transfer request flag
Receive buffer Receive buffer full flag
full (I2C_nINTF.RBFIF)
Transmit buffer Transmit buffer empty
empty flag
(I2C_nINTF.TBEIF)
The I2C provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown above
for the number of DMA channels. A DMA transfer request is sent to the pertinent channel of the DMA controller
only when the DMA transfer request flag, of which DMA transfer has been enabled by the DMA transfer request
enable bit, is set. The DMA transfer request flag also serves as an interrupt flag, therefore, both the DMA trans-
fer request and the interrupt cannot be enabled at the same time. After a DMA transfer has completed, disable the
DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA
control, refer to the "DMA Controller" chapter.

16.7 Control Registers

I2C Ch.n Clock Control Register

Register name Bit
I2C_nCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
16-18
SDA
SCL
TXSTOP = 1
RXD[7:0] read (during reception)
SDA
SCL
Figure 16.5.1 START/STOP Condition Interrupt Timings
Table 16.6.1 DMA Transfer Request Causes of I2C
When received data is loaded to the re-
ceive data buffer
Master mode: When a START condition is
issued or when an ACK is received from the
slave
Slave mode: When transmit data written to
the transmit data buffer is transferred to the
shift register or when an address match is
detected with R/W bit set to 1
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0
0x0
Seiko Epson Corporation
(BRT + 3) × 3
f
CLK_I2Cn
TXSTOP = 0
STOPIF = 1
BSY = 0
STOPIF = 1
Set condition
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
Clear condition
Reading received data (to
empty the receive data buffer),
software reset
Writing transmit data
Remarks
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)