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SPIA Ch.n Transmit Data Register
Register name
Bit
SPIA_nTXD
15–0 TXD[15:0]
Bits 15–0 TXD[15:0]
Data can be written to the transmit data buffer through these bits.
In master mode, writing to these bits starts data transfer.
Transmit data can be written when the SPIA_nINTF.TBEIF bit = 1 regardless of whether data is being
output from the SDOn pin or not.
Note that the upper data bits that exceed the data bit length configured by the SPIA_nMOD.
CHLN[3:0] bits will not be output from the SDOn pin.
Note: Be sure to avoid writing to the SPIA_nTXD register when the SPIA_nINTF.TBEIF bit = 0. Other-
wise, transfer data cannot be guaranteed.
SPIA Ch.n Receive Data Register
Register name
Bit
SPIA_nRXD
15–0 RXD[15:0]
Bits 15–0 RXD[15:0]
The receive data buffer can be read through these bits. Received data can be read when the SPIA_
nINTF.RBFIF bit = 1 regardless of whether data is being input from the SDIn pin or not. Note that the
upper bits that exceed the data bit length configured by the SPIA_nMOD.CHLN[3:0] bits become 0.
SPIA Ch.n Interrupt Flag Register
Register name
Bit
SPIA_nINTF
15–8 –
7
6–4 –
3
2
1
0
Bits 15–8 Reserved
Bit 7
BSY
This bit indicates the SPIA operating status.
1 (R):
Transmit/receive busy (master mode), #SPISSn = Low level (slave mode)
0 (R):
Idle
Bits 6–4
Reserved
Bit 3
OEIF
Bit 2
TENDIF
Bit 1
RBFIF
Bit 0
TBEIF
These bits indicate the SPIA interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag (OEIF, TENDIF)
0 (W):
Ineffective
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name
Initial
0x0000
Bit name
Initial
0x0000
Bit name
Initial
0x00
BSY
0
0x0
OEIF
0
TENDIF
0
RBFIF
0
TBEIF
1
Seiko Epson Corporation
14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Reset
R/W
H0
R/W
–
Reset
R/W
H0
R
–
Reset
R/W
–
R
–
H0
R
–
R
H0/S0
R/W
Cleared by writing 1.
H0/S0
R/W
H0/S0
R
Cleared by reading the
SPIA_nRXD register.
H0/S0
R
Cleared by writing to the
SPIA_nTXD register.
Remarks
Remarks
Remarks
14-15
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