Svd3 Reset; Control Registers; Svd3 Clock Control Register - Epson Arm S1C31 Series Technical Manual

Once the SVD3INTF.SVDIF bit is set, it will not be cleared even if the power supply voltage subsequently returns
to a value exceeding the SVD detection voltage V
due to a temporary power supply voltage drop, check the power supply voltage status by reading the SVD3INTF.
SVDDT bit in the interrupt handler routine.

11.5.2 SVD3 Reset

Setting the SVD3CTL.SVDRE[3:0] bits to 0xa allows use of the SVD3 reset issuance function.
The reset issuing timing is the same as that of the SVD3INTF.SVDIF bit being set when a low voltage is detected.
After a reset has been issued, SVD3 enters continuous operation mode even if it was operating in intermittent op-
eration mode, and continues operating. Issuing an SVD3 reset initializes the port assignment. However, when EXS-
VDn is being detected, the input of the port for the EXSVDn pin is sent to SVD3 so that SVD3 will continue the
EXSVDn detection operation.
If the power supply voltage reverts to the normal level, the SVD3INTF.SVDDT bit goes 0 and the reset state is can-
celed. After that, SVD3 resumes operating in the operation mode set previously via the initialization routine.
During reset state, the SVD3 control bits are set as shown in Table 11.5.2.1.
Control register
SVD3CLK
SVD3CTL
SVD3INTF
SVD3INTE

11.6 Control Registers

SVD3 Clock Control Register

Register name Bit
SVD3CLK 15–9 –
8
7
6–4 CLKDIV[2:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the SVD3 operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bit 7 Reserved
Bits 6–4 CLKDIV[2:0]
These bits select the division ratio of the SVD3 operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of SVD3.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
SVD
Table 11.5.2.1 SVD3 Control Bits During Reset State
Control bit
DBRUN Reset to the initial values.
CLKDIV[2:0]
CLKSRC[1:0]
VDSEL The set value is retained.
SVDSC[1:0] Cleared to 0. (The set value becomes invalid as SVD3
enters continuous operation mode.)
SVDC[4:0] The set value is retained.
SVDRE[3:0] The set value (0xa) is retained.
EXSEL The set value is retained.
SVDMD[1:0] Cleared to 0 to set continuous operation mode.
MODEN The set value (1) is retained.
SVDIF The status (1) before being reset is retained.
SVDIE Cleared to 0.
Bit name Initial
0x00
DBRUN 1
– 0
0x0
0x0
0x0
Seiko Epson Corporation
11 SUPPLY VOLTAGE DETECTOR (SVD3)
/EXSVD detection voltage V
Setting
Reset R/W
– R –
H0 R/WP
– R
H0 R/WP
– R
H0 R/WP
. An interrupt may occur
SVD_EXT
Remarks
11-5