Epson Arm S1C31 Series Technical Manual page 198

Data receiving operations (8/16-bit read)
The 8 and 16-bit read operations are the same as the 32-bit read operation except that data are not prefetched
into the FIFO.
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
QSPI_nMOD register
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
QSPI_nMOD register
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
n
2
0/1
Address cycle
(high-order 8/16 bits)
Dummy cycle
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Address cycle
(low-order 16 bits)
n
Data cycle
Dummy
cycle
15-21