Epson Arm S1C31 Series Technical Manual page 287

(1) One-time conversion mode (ADC12A_nTRG.CNVMD bit = 0)
A/D conversion for ADINn0 (ADC12A_nTRG.STAAIN[2:0] bits = 0x0, ADC12A_nTRG.ENDAIN[2:0] bits = 0x0)
External trigger (ADC12A_nTRG.CNVTRG[1:0] bits = 0x3)
ADC12A_nCTL.ADST
#ADTRGn pin (trigger)
ADC12A_nCTL.BSYSTAT
ADC12A_nCTL.ADSTAT[2:0]
A/D conversion operations
ADC12A_nADD.ADD[15:0]
ADC12A_nINTF.AD0CIF
ADC12A_nINTF.OVIF
(2) One-time conversion mode (ADC12A_nTRG.CNVMD bit = 0)
A/D conversion for ADINn2–4 (ADC12A_nTRG.STAAIN[2:0] bits = 0x2, ADC12A_nTRG.ENDAIN[2:0] bits = 0x4)
External trigger (ADC12A_nTRG.CNVTRG[1:0] bits = 0x3)
ADC12A_nCTL.ADST
#ADTRGn pin (trigger)
ADC12A_nCTL.BSYSTAT
ADC12A_nCTL.ADSTAT[2:0]
A/D conversion operations
ADC12A_nADD.ADD[15:0]
ADC12A_nINTF.AD2CIF
ADC12A_nINTF.AD3CIF
ADC12A_nINTF.AD4CIF
ADC12A_nINTF.OVIF
(3) Continuous conversion mode (ADC12A_nTRG.CNVMD bit = 1)
A/D conversion for ADINn3–4 (ADC12A_nTRG.STAAIN[2:0] bits = 0x3, ADC12A_nTRG.ENDAIN[2:0] bits = 0x4)
Software trigger (ADC12A_nTRG.CNVTRG[1:0] bits = 0x0)
ADC12A_nCTL.ADST
ADC12A_nCTL.BSYSTAT
ADC12A_nCTL.ADSTAT[2:0]
A/D conversion operations
ADC12A_nADD.ADD[15:0]
ADC12A_nINTF.AD3CIF
ADC12A_nINTF.AD4CIF
A/D converted data transfer using DMA
By setting the ADC12A_nDMAEN.ADCDMAENx bit to 1 (DMA transfer request enabled), a DMA trans-
fer request is sent to the DMA controller and the ADC12A_nADD register value is transferred to the speci-
fied memory via DMA Ch.x when the ADC12A_nINTF.ADmCIF bit is set to 1 (when A/D conversion for
the analog input signal m has completed).
This automates reading and saving of A/D converted data.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the
"DMA Controller" chapter.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
A/D converting
0x0 (ADINn0) 0x1 (ADINn1)
Sampling Conversion
ADINn0 ADINn0
ADINn0 conversion result (first)
A/D converting
0x2 (ADINn2) 0x3 (ADINn3)
Sampling Conversion Sampling Conversion
ADINn2 ADINn2 ADINn3 ADINn3
ADINn2 conversion result ADINn3 conversion result
0x3 (ADINn3) 0x4 (ADINn4)
Sampling Conversion Sampling Conversion
ADINn3 ADINn3 ADINn4 ADINn4
First ADINn3 result
Figure 19.4.4.1 A/D Conversion Operations
Seiko Epson Corporation
19 12-BIT A/D CONVERTER (ADC12A)
A/D converting
0x0 (ADINn0) 0x1 (ADINn1)
Sampling Conversion
ADINn0 ADINn0
ADINn0 conversion result (second)
Cleared
Invalid trigger
0x4 (ADINn4) 0x5 (ADINn5)
Sampling Conversion
ADINn4 ADINn4
Cleared
Overwrite
A/D converting
0x3 (ADINn3) 0x4 (ADINn4)
Sampling Conversion Sampling Conversion
ADINn3 ADINn3 ADINn4
First ADINn4 result Second ADINn3 result
Cleared
Cleared
A/D converting
0x0 (ADINn0)
Sampling Conversion
ADINn0 ADINn0
Overwrite
ADINn4 conversion result
0x5 (ADINn5)
ADINn4
Second ADINn4 result
Cleared
Cleared
19-5