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4 MEMORY AND BUS
Peripheral circuit
R/F converter (RFC) Ch.1
16-bit timer (T16) Ch.3
12-bit A/D converter (ADC12A)
Operational amplifier/comparator
(OPCMP)
4.6.1 System-Protect Function
The system-protect function protects control registers and bits from writings. They cannot be rewritten unless write
protection is removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits. This function is provided to prevent
deadlock that may occur when a system-related register is altered by a runaway CPU. See "Control Registers" in
each peripheral circuit to identify the registers and bits with write protection.
Note: Once write protection is removed using the MSCPROT.PROT[15:0] bits, write enabled status is
maintained until write protection is applied again. After the registers/bits required have been al-
tered, apply write protection.
4.7 Control Registers
MISC System Protect Register
Register name
Bit
MSCPROT
15–0 PROT[15:0]
Bits 15–0 PROT[15:0]
These bits protect the control registers related to the system against writings.
0x0096 (R/W):
Other than 0x0096 (R/W): Enable system protection
While the system protection is enabled, any data will not be written to the affected control bits (bits
with "WP" or "R/WP" appearing in the R/W column).
4-8
Address
0x546a RFC1TCL
0x546c RFC1TCH
0x546e RFC1INTF
0x5470 RFC1INTE
0x5480 T16_3CLK
0x5482 T16_3MOD
0x5484 T16_3CTL
0x5486 T16_3TR
0x5488 T16_3TC
0x548a T16_3INTF
0x548c T16_3INTE
0x54a2 ADC12_0CTL
0x54a4 ADC12_0TRG
0x54a6 ADC12_0CFG
0x54a8 ADC12_0INTF
0x54aa ADC12_0INTE
0x54ac ADC12_0AD0D
0x54ae ADC12_0AD1D
0x54b0 ADC12_0AD2D
0x54b2 ADC12_0AD3D
0x54b4 ADC12_0AD4D
0x54b6 ADC12_0AD5D
0x54e2 OPCMPMOD
0x54e4 OPCMP0CTL
0x54e6 OPCMP1CTL
Bit name
Initial
0x0000
Disable system protection
Seiko Epson Corporation
Register name
RFC Ch.1 Time Base Counter Low Register
RFC Ch.1 Time Base Counter High Register
RFC Ch.1 Interrupt Flag Register
RFC Ch.1 Interrupt Enable Register
T16 Ch.3 Clock Control Register
T16 Ch.3 Mode Register
T16 Ch.3 Control Register
T16 Ch.3 Reload Data Register
T16 Ch.3 Counter Data Register
T16 Ch.3 Interrupt Flag Register
T16 Ch.3 Interrupt Enable Register
ADC12A Ch.0 Control Register
ADC12A Ch.0 Trigger/Analog Input Select Register
ADC12A Ch.0 Configuration Register
ADC12A Ch.0 Interrupt Flag Register
ADC12A Ch.0 Interrupt Enable Register
ADC12A Ch.0 Result Register 0
ADC12A Ch.0 Result Register 1
ADC12A Ch.0 Result Register 2
ADC12A Ch.0 Result Register 3
ADC12A Ch.0 Result Register 4
ADC12A Ch.0 Result Register 5
OPCMP Mode Register
OPCMP Ch.0 Control Register
OPCMP Ch.1 Control Register
Reset
R/W
H0
R/W
–
S1C17W22/W23 TECHNICAL MANUAL
Remarks
(Rev. 1.3)
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