P5 Port Group - Epson S1C17W18 Technical Manual

6 I/O PORTS (PPORT)

6.7.6 P5 Port Group

The P5 port group consists of three ports P50–P52 and they support the GPIO and interrupt functions.
Note: The P5 port group does not exist in the 64-pin and 80-pin packages.
Register name Bit
P5DAT 15–11 –
(P5 Port Data
10–8 P5OUT[2:0]
Register)
7–3 –
2–0 P5IN[2:0]
P5IOEN 15–11 –
(P5 Port Enable
10–8 P5IEN[2:0]
Register)
7–3 –
2–0 P5OEN[2:0]
P5RCTL 15–11 –
(P5 Port Pull-up/down
10–8 P5PDPU[2:0]
Control Register)
7–3 –
2–0 P5REN[2:0]
P5INTF 15–8 –
(P5 Port Interrupt
7–3 –
Flag Register)
2–0 P5IF[2:0]
P5INTCTL 15–11 –
(P5 Port Interrupt
10–8 P5EDGE[2:0]
Control Register)
7–3 –
2–0 P5IE[2:0]
P5CHATEN 15–8 –
(P5 Port Chattering
7–3 –
Filter Enable Register)
2–0 P5CHATEN[2:0]
P5MODSEL 15–0 –
(P5 Port Mode Select
Register)
P5FNCSEL 15–0 –
(P5 Port Function
Select Register)
P5SELy = 0
Port
name
GPIO
Peripheral
P50 P50
P51 P51
P52 P52
6-16
Table 6.7.6.1 Control Registers for P5 Port Group
Bit name Initial
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x00
0x0
0x0000
0x0000
Table 6.7.6.2 P5 Port Group Function Assignment
P5yMUX = 0x0 P5yMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
– – –
– – –
– – –
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
– R
H0 R
– R –
H0 R/W
– R
H0 R/W
– R –
H0 R/W
– R
H0 R/W
– R –
– R
H0 R/W Cleared by writing 1.
– R –
H0 R/W
– R
H0 R/W
– R –
– R
H0 R/W
– R –
– R –
P5SELy = 1
P5yMUX = 0x2
(Function 2)
Pin Peripheral Pin
– – –
– – –
– – –
S1C17W18 TECHNICAL MANUAL
Remarks
P5yMUX = 0x3
(Function 3)
Peripheral Pin
– –
– –
– –
(Rev. 1.2)