Table of Contents
Advertisement
Figure 6.24 Reducing short-cycle oscillation diagram.
If oscillation cannot be reduced even by setting the differential time to 0, then either lower the
proportional gain or raise the PID primary delay time constant.
Function
Code
P9.07
Sampling cycle (T)
P9.08
Sampling cycle T refers to the sampling cycle of feedback value. The PI regulator
calculates once in each sampling cycle. The bigger the sampling cycle, the slower the
response is.
Bias limit defines the maximum bias between the feedback and the preset. PID stops
operation when the bias is within this range. Setting this parameter correctly is helpful to
improve the system output accuracy and stability.
Name
Description
0.01~100.00s
Bias limit
0.0~100.0%
Setting Range
0.01~100.00
0.0~100.0
70
Factory
Setting
0.10s
0.0%
Advertisement
Table of Contents
