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Epson Research and Development
Vancouver Design Center
7 A.C. CHARACTERISTICS
Conditions : V
7.1 Bus Interface Timing
7.1.1 MC68000 Interface Timing
Note
All input timing parameters are based on a maximum 16MHz MPU clock.
IOW# Timing
AB[9:1]
IOCS#
UDS#/LDS#
DTACK#
DB[15:0]
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Hardware Functional Specification
Issue Date: 01/01/29
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= 3.0V ± 10%, V
DD
DD
T
and T
for all inputs must be < 5 nsec (10% ~ 90%)
rise
fall
C
= 80pF (Bus/MPU Interface)
L
C
= 100pF (LCD Panel Interface)
L
C
= 20pF (Display Memory Interface)
L
AS#
t1
R/W
INVALID
Hi-Z
Table 7-1: IOW# Timing (MC68000)
Parameter
AB[9:1] valid before AS# falling edge
AB[9:1] hold from AS# rising edge
IOCS# hold from AS# rising edge
UDS#/LDS# valid before AS# rising edge
UDS#/LDS# falling edge to DTACK# falling edge
AS# rising edge to DTACK# hi-z delay
DB[15:0] setup to AS# rising edge
DB[15:0] hold from AS# rising edge
= 3.3V ± 10%, or V
= 5.0V ± 10% T
DD
VALID
t4
t5
Hi-Z
Figure 10: IOW# Timing (MC68000)
= -40 °C to 85 °C
A
t2
t3
t6
Hi-Z
t8
t7
VALID
3V/3.3V
5V
Min Max Min Max
10
0
20
10
0
0
30
20
40
25
40
25
20
10
20
10
Page 29
Hi-Z
Units
ns
ns
ns
ns
ns
ns
ns
ns
S1D13503
X18A-A-001-08
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