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Dynamic TMIN Control Register 1 (Reg. 0X36) <1>
VCCPLO = 1
When the V
voltage drops below the V
CCP
following occurs:
1.
Status Bit 1 (V
) in Status Register 1 is set.
CCP
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
4.
Dynamic T
control is disabled. This prevents T
MIN
being adjusted due to an S3 or S5 state.
5.
The ADT7473 is prevented from entering the shutdown
state.
Once the core voltage, V
, goes above the V
CCP
everything is re-enabled, and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7473 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
Figure 42 shows the signals that are exercised in the XNOR tree
test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (Reg. 0x6F).
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
Figure 42. XNOR Tree Test
low limit, the
CCP
from
MIN
low limit,
CCP
PWM1/XTO
Rev. 0 | Page 31 of 76
POWER-ON DEFAULT
When the ADT7473 is powered up, it polls the V
If V
stays below 0.75 V (the system CPU power rail is not
CCP
powered up), the ADT7473 assumes the functionality of the
default registers after the ADT7473 is addressed via any valid
SMBus transaction.
If V
goes high (the system processor power rail is powered
CC
up), a fail-safe timer begins to count down. If the ADT7473 is
not addressed by any valid SMBus transactions before the fail-
safe timeout (4.6 sec) lapses, the ADT7473 drives the fans to full
speed. If the ADT7473 is addressed by a valid SMBus
transaction after this point, the fans stop, and the ADT7473
assumes its default settings and begins normal operation.
If VCCP goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7473 is addressed by a valid SMBus transaction before the
fail-safe timeout (4.6 sec) lapses, then the ADT7473 operates
normally, assuming the functionality of all the default registers.
See the flow chart in Figure 43.
ADT7473 IS POWERED UP
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
Y
SMBus TRANSACTION?
N
IS V
ABOVE 0.75V?
CCP
Y
START FAIL-SAFE TIMER
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
Y
SMBus TRANSACTION?
N
FAIL-SAFE TIMER ELAPSES
AFTER THE FAIL-SAFE TIMEOUT
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
Y
START UP THE
ADT7473 NORMALLY
Figure 43. Power-On Flow Chart
ADT7473
input.
CCP
CHECK V
CCP
N
RUNS THE FANS
TO FULL SPEED
N
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
Y
SWITCH OFF FANS
N
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