Table 40. PWM Duty Cycle Registers
Register
Description
0x30
PWM1 duty cycle
0x31
PWM2 duty cycle
0x32
PWM3 duty cycle
By readin he
g t
PWMx current duty
keep
track of th
e current duty c
when
the fans a
re running in automa
or in
aco
ust
ic e
nhancement m
VARY PWM D UTY
CYCLE WITH 8-BIT
RESOLUTION
Figure 5
3. C
ontr
ol PWM Duty Cycle
OPERATING FROM 3.3 V STANDBY
The
ADT 60
74
has been specifically d
3.3 V
STBY sup
ply. In computers tha
the co
re v
oltag of the proces
e
using t
he
dyn
am
ic TMIN mo
the p
roce
ssor ould change
w
the d
ynamics o
f the system under dyna
Likew
ise
, when monitoring THERM , the HERM
be d
isable
d du ing these states.
r
Def
ault
0xFF (100%)
0xFF (100%)
0xFF (100%)
cycle gisters, users c
re
ycle on ea
ch
PWM output ven
tic f
an
speed
co
ntrol ode
ode.
Manually w
ith
a Reso
lut
ion of 0
esig
ned
to o
pera
te fr
t sup rt S3
po
and
S5 s es,
sor is lower
ed
in the states
se
de, lowerin he cor
g t
e v
oltage f
the CPU tem
per
atur
e a
nd cha e
mic TMIN contro
timer s uld
T
XNOR TREE TEST MODE
The ADT7460 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
p
ossib to de
le
F ure 54 shows t
ig
an
t
est
mod
e.
, e
T
he
XN
OR
m
XNOR t
ree
.39
%
POWER-ON DEFAULT
The ADT7460 does not monitor temperatu
d
efaul n po
t o
om
a
i
s enab d by s ing t
le
tat
( t 0, A ress 0x40) to 1. The
Bi
dd
. If
u
p. This is
becaus the BHVR b
o
c
onf
igur
atio
ng
default.
l.
ho
Rev. C | Page 33 of 52
tec
t open
s or shor
ts on t
he sy
he s
ignals tha
t ar
e exercis
tree t t is invoked
es
by set
ting B
test enable register (Reg. 0x6F)
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
PWM1/XTO
Figure 54. X
NOR Tr
ee Test
wer
-up. M
onitorin
g of t
emper
ett
he start bi
t in c
onfigu
fan
s run at f
e
its
(Bits <7
n reg ers are set t
ist
o 1
00 (fans r
ADT7460
stem bo
ard.
ed in
the XN R tree
O
it 0 (X
EN) o he
f t
.
re an
d fan speed by
ature
and fa
n spe
ed
ratio
n Regist r 1
e
ull sp
eed on ower-
p
:5>) in
the PWMx
un fu
ll speed) by
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