Interrupt Requests - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
16.3.2

Interrupt Requests

2
The I C bus interface has six interrupt requests when the I
synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I
Since these interrupt requests are allocated at the I
by each bit is necessary.
Table 16.7 Interrupt Requests of I
Interrupt Request
Transmit data empty
Transmit ends
Receive data full
Stop condition detection
NACK detection
Arbitration lost/overrun error
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
When the generation conditions listed in Table 16.7 are met, an I
Set the interrupt generation conditions to 0 by the I
TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by
further setting the TDRE bit to 0, 1 additional byte may be transmitted.
Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
2
C bus Interface.
2
C bus Interface
TXI TIE = 1 and TDRE = 1
TEI TEIE = 1 and TEND = 1
RXI RIE = 1 and RDRF = 1
STPI STIE = 1 and STOP = 1
NAKI NAKIE = 1 and AL = 1 (or
NAKIE = 1 and NACKF = 1)
Page 210 of 315
16. Clock Synchronous Serial Interface
2
C bus format is used and four when the clock
2
C bus interface interrupt vector table, determining the factor
Generation Condition
2
C bus interface interrupt request is generated.
2
C bus interface interrupt routine. However, bits TDRE and
Format
2 Clock
I C bus
Synchronous
Serial
Enabled Enabled
Enabled Enabled
Enabled Enabled
Enabled Disabled
Enabled Disabled
Enabled Enabled