Precautions On Clock Synchronous Serial Interface; Notes On Clock Synchronous Serial I/O With Chip Select - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
20.5

Precautions on Clock Synchronous Serial Interface

20.5.1

Notes on Clock Synchronous Serial I/O with Chip Select

Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
20.5.1.1 Accessing Registers Associated with Clock Synchronous Serial I/O
with Chip Select
After waiting three instructions or more after writing to the registers associated with clock synchronous serial I/
O with chip select (00B8h to 00BFh) or four cycles or more after writing to them, read the registers.
• An example of waiting three instructions or more
Program example
• An example of waiting four cycles or more
Program example
20.5.1.2 Selecting SSI Signal Pin
Set the SOOS bit in the SSMR2 register to 0 (CMOS output) in the following settings:
• SSUMS bit in SSMR2 register = 1 (4-wire bus communication mode)
• BIDE bit in SSMR2 register = 0 (standard mode)
• MSS bit in SSCRH register = 0 (operate as slave device)
• SSISEL bit in PMR register = 1 (use P1_6 pin for SSI01 pin)
Do not use the SSI01 pin with NMOS open drain output for the above settings.
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
MOV.B
NOP
NOP
NOP
MOV.B
BCLR
JMP.B
NEXT:
BSET
Page 303 of 315
#00h,00BBh ; Set the SSER register to 00h.
00BBh,R0L
4,00BBh : Disable transmission
NEXT
3,00BBh : Enable reception
20. Usage Notes