Xilinx EK-VCK190-G-ED Manuals

Manuals and User Guides for Xilinx EK-VCK190-G-ED. We have 1 Xilinx EK-VCK190-G-ED manual available for free PDF download: User Manual

Xilinx EK-VCK190-G-ED User Manual

Xilinx EK-VCK190-G-ED User Manual (80 pages)

Brand: Xilinx | Category: Motherboard | Size: 3.86 MB

Table of Contents

Revision History

2
- Table of Contents
  3
- Overview
  5
Chapter 1: Introduction

5
- Navigating Content by Design Process
  6
  - Models of VCK190 Boards
    6
  - Versal ACAP Kit Numbering
    6
- Additional Resources
  7
- Block Diagram
  8
- Board Features
  9
- Board Specifications
  12
  - Dimensions (Extended Height Pcie Form-Factor)
    12
  - Environmental
    12
- Standard ESD Measures
  13
- Board Component Location
  13
Chapter 2: Board Setup and Configuration

13
- Evaluation Board Component Locations
  14
- Board Component Descriptions
  15
- Board Component Locations
  15
- Default Jumper and Switch Settings
  17
  - Board Jumper Header and Switch Locations
    18
  - Default Jumper Settings
    18
  - Jumpers
    18
  - Default Switch Settings
    20
  - Switches
    20
  - Jtag
    21
  - Mode Switch SW1 Configuration Option Settings
    21
- Versal ACAP Configuration
  21
  - Qspi32
    22
  - Sd1_3.0
    22
- Component Descriptions
  23
  - Encryption Key Battery Backup Circuit
    23
  - Versal ACAP
    23
Chapter 3: Board Component Descriptions

23
- Overview
  23
  - I/O Voltage Rails
    24
  - Encryption Key Backup Circuit
    24
  - DDR4 UDIMM Socket
    25
  - DDR4 DIMM Memory
    25
  - LPDDR4 Component Memory
    26
  - System Reset POR_B
    27
  - PMC and LPD MIO
    28
  - MIO Peripheral Mapping
    28
  - POR_B Reset Circuit
    28
  - PMC MIO[13:25] Bank 500: USB 2.0 ULPI PHY
    30
  - MIO Connector J212 Pinout
    30
  - IP4856CX25 U104 Adapter Pinout
    32
  - PS MIO[37] ZU4 System Controller GPIO
    33
  - PMC MIO[38:39] Pcie Status
    33
  - I2C0 and I2C1 Bus Connectivity Overview
    36
  - I2C0 Bus Topology
    37
  - I2C1 Bus Topology
    40
  - I2C1 TCA9548A U35 Address 0X74 Connections
    40
  - GEM1 Ethernet
    42
  - Ethernet PHY (Three Resets)
    42
  - Ethernet PHY Reset Circuit
    43
  - Ethernet PHY LED Interface
    43
  - Ethernet PHY LED Functional Description
    43
  - JTAG Chain
    44
  - JTAG Chain Block Diagram
    44
  - Clock Generation
    45
  - Clock Sources
    45
  - Programmable DDR4 DIMM SI570 Clock
    45
  - Programmable LPDDR4 SI570 Clock2
    46
  - Programmable LPDDR4 SI570 Clock1
    46
  - Programmable HSDP SI570 Clock
    47
  - Programmable Zsfp SI570 Clock
    47
  - Programmable SI570 REF Clock
    47
  - Programmable SI5332 System Controller Clock
    48
  - Pcie Clock
    49
  - Programmable FMCP MGT SI570 Clock with Buffer
    49
  - IEEE-1588 Ecpri Programmable Synchronization Management Unit
    50
  - GTY Transceivers
    50
  - VCK190 GTY Connections
    52
  - GTY103/104: PCI Express Card Edge Connectivity
    52
  - Zsfp/Zsfp+ Module Connector
    53
  - GTY105: HSDP and 2X Zsfp
    53
  - Gty200: Qsfp1
    55
  - QSFP Module Connector
    55
  - GTY106: HDMI TX and RX
    56
  - HDMI Video Output (TX)
    56
  - HDMI Interface Block Diagram
    57
  - FPGA Mezzanine Card Interface
    58
  - FMC+ Connector Type
    58
  - FMCP1 Connector J51
    59
  - FMCP2 Connector J53
    59
  - VADJ_FMC Power Rail
    60
  - User I/O
    60
  - Power and Status Leds
    60
  - Cooling Fan Connector
    62
  - Power Good Indicator Leds
    62
  - System Controller
    63
  - 12V Fan Header
    63
  - System Controller User Interface
    64
  - Power On/Off Slide Switch
    65
  - Power System - Pmbus Regulators and INA226 Map
    66
  - Device Rail Maximum Current
    66
  - Power System - Non-Pmbus Regulators and INA226 Map
    67
  - Monitoring Voltage and Current
    68
Appendix A: VITA 57.4 FMCP Connector Pinouts

69
- Overview
  69
Appendix B: Xilinx Design Constraints

70
- Overview
  70
Appendix C: Pmod FMC

71
- Pin Mapping Pmod to FMC
  72
  - TXS0108E Bidirectional Voltage Level Translator
    72
  - Pmod FMC Pin Mapping
    73
Appendix D: Regulatory and Compliance Information

74
- CE Information
  74
- Compliance Markings
  75
Appendix E: Additional Resources and Legal Notices

76
- Xilinx Resources
  76
- Documentation Navigator and Design Hubs
  76
- References
  77
- Please Read: Important Legal Notices
  78

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