Xilinx ZC702 User Manual page 50

PMOD connectors J62 and J63 are wired to the U1 XC7Z020 SoC via TXS0108E 3.3V-to-VADJ
(typically 1.8V) level-shifters.
Figure 1-25 shows the user GPIO male pin header circuits.
X-Ref Target - Figure 1-25
J62
When using the PMOD headers on the Zynq-7000 SoC ZC702 evaluation kit, the voltage
level output might appear normal at steady state; however, the rise and fall times on the
other side of the TXS0108E level shifters can be several microseconds. The paralleled LED
driver NDS331N FET has a gate capacitance of ~200 pF. The 200 pF load affects maximum
toggle rate, which is ~100 kHz. There are no speed requirements for PMOD or GPIOs. The
recommendation for a specific high-speed access with GPIO is to use the FMC interface.
Table 1-27 lists the GPIO Header connections to XC7Z020 SoC U1.
Table 1-27: GPIO Header Connections to XC7Z020 SoC at U1
XC7Z020 (U1) Pin
E15
D15
W17
W5
V7
W10
P18
P17
Refer to the Zynq-7000 SoC Technical Reference Manual (UG585)
about the PS PJTAG functionality.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
VCC3V3
1 PMOD2 0
PMOD2 1
2
3 PMOD2 2
PMOD2 3
4
5
6
GND
Figure 1-25: User GPIO Headers
Net Name I/O Standard
PMOD1_0
PMOD1_1
PMOD1_2
PMOD1_3
PMOD2_0
PMOD2_1
PMOD2_2
PMOD2_3
www.xilinx.com
VCC3V3 VCC3V3
J63
PMOD1 0 1 2
PMOD1 1 3 4
PMOD1 2 5 6
7 8
PMOD1 3
9 10
11 12
GND GND
GPIO Header and Pin
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
Feature Descriptions
PL PJTAG TDI LS
PL PJTAG TMS LS
PL PJTAG TCK LS
PL PJTAG TDO LS
UG850_c1_25_030513
J63.1
J63.3
J63.5
J63.7
J62.1
J62.2
J62.3
J62.4
[Ref 2] for information
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