Xilinx ZC702 User Manual page 23

The USB3320 is clocked by a 24 MHz crystal. Consult the Standard Microsystems
Corporation (SMSC) USB3320 data sheet for clocking mode details
The interface to the USB3320 transceiver is implemented through the IP in the XC7Z020 SoC
Processor System.
Table 1-6 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the
default shunt positions for USB 2.0 high speed on-the-go (OTG) mode.
Table 1-6: USB Jumper Settings
Header Function
J44 USB PHY reset
J7 VBUS 5V
supply
J33 RVBUS select
J35 CVBUS select
J34 Cable ID select
J36 USB Micro-B
The connections between the USB Mini-B connector at J1 and the PHY at U9 are listed in
Table 1-7.
Table 1-7: USB Connector Pin Assignments and Signal Definitions Between J1 and U9
USB Connector
J1
Pin Name
1 VBUS USB_VBUS_SEL
2 D_N USB_D_N
3 D_P USB_D_P
5 GND GND
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Shunt Position
Shunt ON = USB PHY reset
Shunt OFF = USB PHY normal operation
Shunt ON = Host or OTG mode
Shunt OFF = Device mode
Position 1–2 = Device mode (10 k
Position 2–3 = OTG mode (1 kΩ )
Position 1-2 = OTG and Device mode (1
Position 2-3 = Host mode (120 μ F)
Position 1-2 = A/B cable detect
Position 2-3 = ID not used
Position 1-2 = Shield connected to GND
Position 2-3 = Shield floating
Net Name
+5V from host system
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
www.xilinx.com
[Ref
Clean reset requires external
debouncing
) Overvoltage protection
Ω
F) VBUS load capacitance
μ
Used in OTG mode.
Description
Send Feedback
Feature Descriptions
15].
Notes
USB3320 (U9)
Pin
22
19
18
33
23