Xilinx ZC702 User Manual page 15

The PS integrates two Arm® Cortex™-A9 MPCore™ application processors, AMBA®
interconnect, internal memories, external memory interfaces, and peripherals including
USB, Ethernet, SPI, SD/SDIO, I2C, CAN, UART, and GPIO. The PS runs independently of the PL
and boots at power-up or reset.
A system level block diagram is shown in
X-Ref Target - Figure 1-4
Zynq-7000 SoC
Processing System
I/O
Peripherals
Clock
Generation
USB
2x USB
USB
2x GigE
GigE
GigE 2x SD
SD
SDIO
IRQ
SD
SDIO
GPIO
UART
UART
CAN
CAN
I2C
I2C
SPI
SPI
Memory
Interfaces
SRAM/
NOR
ONFI 1.0
NAND
Q-SPI
CTRL
EMIO
XADC
12-Bit ADC
Notes:
1) Arrow direction shows control (master to slave)
2) Data flows in both directions:
For additional information on Zynq-7000 SoC devices, see the Zynq-7000 SoC Data Sheet:
Overview (DS190)
[Ref 2] for more information about Zynq-7000 SoC configuration options.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Reset
SWDT
TTC
System-
Level
Control
Regs
DMA 8
Channel
Central
Interconnect
General-Purpose DMA
Ports Sync
AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit,
Figure 1-4: Zynq-7000 SoC Block Diagram
[Ref 1] and the Zynq-7000 SoC Technical Reference Manual (UG585)
,
www.xilinx.com
Figure 1-4.
Application Processor Unit
FPU and NEON Engine
ARM Cortex-A9
MMU
CPU
32 KB 32 KB
I-Cache D-Cache
Snoop Controller, AWDT, Timer
GIC
512 KB L2 Cache and Controller
256K
OCM
Interconnect
SRAM
CoreSight
Components
DAP
Programmable Logic to
DevC
Memory Interconnect
Config
IRQ High-Performance Ports
AES/
Programmable Logic
SHA
AHB 32-Bit, APB 32-Bit, Custom
Feature Descriptions
FPU and NEON Engine
ARM Cortex-A9
MMU
CPU
32 KB 32 KB
I-Cache D-Cache
Memory
Interfaces
DDR2/3,
LPDDR2
Controller
ACP
SelectIO
Resources
UG850_c1_04_062918
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