Xilinx ZC702 User Manual page 24

The connections between the USB 2.0 PHY at U9 and the XC7Z020 SoC are listed in
Table 1-8.
Table 1-8: USB 2.0 ULPI Transceiver Connections to the XC7Z020 SoC
XC7Z020 (U1)
Pin Name Bank
PS_MIO36 501
PS_MIO31 501
PS_MIO32 501
PS_MIO33 501
PS_MIO34 501
PS_MIO35 501
PS_MIO28 501
PS_MIO37 501
PS_MIO38 501
PS_MIO39 501
PS_MIO30 501
PS_MIO29 501
PS_MIO7 500
Figure 1-7 shows the USB 2.0 ULPI Transceiver circuitry. Note that the shield for the USB
Mini-B connector (J1) can be tied to GND by a jumper on header J36 pins 1–2 (default). The
USB shield can optionally be connected through a capacitor to GND by installing a
capacitor (body size 0402) at location C202 and jumping pins 2-3 on header J36.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Schematic Net Name
Pin Number
A9 USB_CLKOUT
F9
C7 USB_DATA0
G13 USB_DATA1
B12 USB_DATA2
F14 USB_DATA3
A12 USB_DATA4
B14 USB_DATA5
F13 USB_DATA6
C13 USB_DATA7
A11
E8
D5 USB_RESET_B_AND
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USB_NXT
USB_STP
USB_DIR
27 (through AND gate U62)
Feature Descriptions
USB3320 (U9) Pin
1
2
3
4
5
6
7
9
10
13
29
31
24
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