Xilinx ZC702 User Manual page 3

Date Version
04/04/2013 1.2
06/04/2014 1.3
04/30/2015 1.4
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Chapter 1, ZC702 Evaluation Board
Marvell 88E1116R throughout the document. The bullet just before
page 10 changed from PL JTAG header to PS JTAG header. In
PC28F00AG18FE StrataFlash memory changed to 128 Mb, N25Q128A11ESF40G. In
callout 9, Marvell M88E1116R-BAB1C000 changed to 88E1116RA0-NNC1C000.
Callout 30 for J59 and 31 for J60 were added. The
description for callout 1 changed. Callout 29 added a link to
was removed because it is a duplicate of
"configuration option" was changed to "JTAG configuration option." In
the PLL Used mode row was removed and the default setting changed. Section
Encryption Key Backup Circuit, page 17
four I/O banks available on the XC7Z020 SoC" was changed to "There are four PL
I/O banks available on the XC7Z020 SoC." A note about DDR3 memory was added
after Table 1-4. In Quad-SPI Flash Memory
(Micron/Numonyx) changed to N25Q128A11ESF40G. In
"The configuration section of UG585..." was changed to add "The configuration and
QSPI section of UG585..." JTAG information in
updated. In Figure 1-10 pin numbers 5 and 6 are swapped and in U76, IN2 and IN1
switched places. In Table 1-10, SW10 became SW10[1:2] in the table column
heading and the default setting was added. In
frequency jitter changed from 20 ppm to 50 ppm. In
changed to TI. Figure 1-15
Table 1-22, reference designator DS12 changed to DS14. U3 level shifter was
changed to TXS0104E in Figure 1-19
updated. Figure 1-21 added two LEDs.
PS_MIO8_LED0 and removed pin info. Section
Figure 1-26 title changed. A paragraph about design criteria was added to
Management. A paragraph about the TI Fusion Digital Power graphical user
interface precedes Table 1-30. Voltages were added to the description of U19 in
Table 1-30. The TI link on
Appendix A, Default Switch and Jumper
changed from right to left.
Appendix C, Xilinx Design
listing. Minor changes were made to the list, and power and ground pin constraints
were removed.
Appendix D, Board Specifications: This appendix was added to the book.
Appendix E, Regulatory and Compliance
master answer record was added.
Table 1-6 USB Jumper Settings
GND changed to GA0 = 0 = GND in
Master UCF Listing was replaced with the Xilinx Design Constraints (XDC) file listing.
The link in Declaration of Conformity was updated.
Description added to FMC Connector JTAG
Table 1-16, Table 1-17, Table
Table 1-29. Note added to
for U34 from 53 to 54 in Table
File Listing. Added Figure
Table A-2.
www.xilinx.com
Revision
Features: Marvell 88E1111 was changed to
Zynq-7000 XC7Z020 SoC, page 14
Table 1-10. Above
was added. In
and Figure
Figure 1-10
Processing System Clock
is updated. R249 was added to
and Table 1-21. The
Table 1-23 added Net Name PS_LED1 and
User PS Switches
page 62 was updated.
Settings: In
Constraints: A reminder was added to use the latest UCF
Information: A link to the ZC702 board
was updated to highlight default shunt positions.
Table 1-28 and
Bypass. Modifications to
1-23, Table 1-25, Table
Table 1-20. Revised the PMBus Controller–Aux address
1-30. Annotations added to ZC702 Board Constraints
Figure A-1 to identify jumper locations referenced in
Block Diagram,
Table 1-1, callout 3,
Table 1-2. Table 1-2
Table 1-2,
Table 1-2,
I/O Voltage Rails, "There are
1-6, N25Q128A13ESF40F
Quad-SPI Flash Memory,
and Table 1-10 was
Source,
I2C Bus, NXP semiconductor
Figure 1-17. In
User I/O section was
was added. The
Power
Table A-1, SW16 position 4
Table 1-29. The Appendix C
Table 1-12,
1-27, Table 1-28, and
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