Xilinx ZC702 User Manual page 42

Figure 1-19 shows the controller area network (CAN) bus interface.
X-Ref Target - Figure 1-19
VCCMIO
U3
C26
0.1μF
TXS0104E
25V
Bidirectional
X5R
Voltage-Level
Translator
1
GND
VCCA
2
CAN_TXD_LS
A1
3
CAN_RXD_LS
A2
4
CAN_STB_B_LS
A3
5
A4
6
NC1
7
GND
GND
Information about the TXS0104E is available at the Texas Instruments website
sheets and application notes for the TJA01040 CAN transceiver are available at the NXP
Semiconductors website
interface connections through level shifter U3.
Table 1-21: CAN Transceiver SoC Connections
TJA1040 (U14)
Pin Net Name
1 CAN_TXD
4 CAN_RXD
8 CAN_STB_B
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
VCC5V0 VCCMIO
C25
0.1μF
25V
X5R
GND GND
U14
TJA1040
Transceiver
14 3
VCCB
VCC
13 1
CAN TXD
B1
TXD
12 4
CAN RXD
B2
RXD
11 8
CAN STB B
B3
STB
10
B4
9
NC2
8
OE
Figure 1-19: CAN Bus Interface
[Ref 24]. Table 1-21
TXS0104E Level Shifter (U3)
Net Name
CAN_TXD_LS
CAN_RXD_LS
CAN_STB_B_LS
www.xilinx.com
C520
C24 47 μF
0.1μF
10V
25V
X5R
X5R
GND
CAN_CANH
R282
60.4Ω
CAN
5%
7
CANH
6
CANL
5
SPLIT
2
GND
C304
4700 pF
25V
NPO
GND GND
shows the U14 CAN transceiver to U1 XC7Z020
XC7Z020 SoC (U1)
Low Side Net
PS_MIO47
PS_MIO46
PS_MIO9
Feature Descriptions
CAN Interface
Connector
J52
1
3
5
GND
7
2 1 9
J53
C330
18 pF
50V
NPO
GND
CAN_CANL
1
R281 J15
C331
60.4Ω
18 pF
5%
50V
NPO
GND
UG850_c1_19_031913
[Ref 25]. Data
Bank Pin
501 B10
501 D12
500 C4
Send Feedback
2
4
5
8
10
2
42