Table of Contents
Advertisement
Power-on Reset
AT90S2313
20
Figure 23. Reset Logic
Table 3. Reset Characteristics (V
Symbol
Parameter
Power-on Reset Threshold Voltage (rising)
(1)
V
POT
Power-on Reset Threshold Voltage (falling)
V
RESET Pin Threshold Voltage
RST
Reset Delay Time-out Period
t
TOUT
FSTRT Unprogrammed
Reset Delay Time-out Period
t
TOUT
FSTRT Programmed
Note:
1. The Power-on Reset will not work unless the supply voltage has been below V
(falling).
The user can select the start-up time according to typical oscillator start-up. The number
of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of
the Watchdog Oscillator is voltage-dependent, as shown in "Typical Characteristics" on
page 75.
Table 4. Number of Watchdog Oscillator Cycles
FSTRT
Time-out at V
Programmed
0.28 ms
Unprogrammed
16.0 ms
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer
prevents the MCU from starting until after a certain period after V
Power-on Threshold voltage (V
can be programmed to give a shorter start-up time if a ceramic resonator or any other
fast-start oscillator is used to clock the MCU.
If the built-in start-up delay is sufficient, RESET can be connected to V
an external pull-up resistor. By holding the RESET pin low for a period after V
been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a tim-
ing example of this.
= 5.0V)
CC
Min
1.0
0.4
11.0
0.25
= 5V
Number of WDT Cycles
CC
256
16K
) (see Figure 24). The FSTRT Fuse bit in the Flash
POT
Typ
Max
Units
1.4
1.8
V
0.6
0.8
V
–
0.85 V
V
CC
16.0
21.0
ms
0.28
0.31
ms
POT
has reached the
CC
directly or via
CC
has
CC
0839G–08/01
Advertisement
Table of Contents
