Power-On Reset - Atmel ATmega48PV Manual

8.3

Power-on Reset

8025I–AVR–02/09
Figure 8-1. Reset Logic
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
RSTDISBL
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in "System and Reset Characteristics" on page
V is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
CC
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V decreases below the detection level.
CC
Figure 8-2. MCU Start-up, RESET Tied to V
V
CC
RESET
TIME-OUT
INTERNAL
RESET
ATmega48P/88P/168P/328P
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
Watchdog
Oscillator
Clock CK
Generator
CKSEL[3:0]
SUT[1:0]
rise. The RESET signal is activated again, without any delay,
CC
CC
V
POT
V
RST
t
TOUT
Delay Counters
TIMEOUT
320. The POR is activated whenever
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