Block Diagram - Atmel AVR ATmega103 Manual

Block Diagram

ATmega103(L)
4
Figure 1. The ATmega103(L) Block Diagram
PF0 - PF7
VCC
GND
PORTF BUFFERS
AVCC
ANALOG MUX
AGND
AREF
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
DATA REGISTER
PORTE
PORTE DRIVER/BUFFERS
PE0 - PE7
PA0 - PA7
PORTA DRIVER/BUFFERS
DATA REGISTER DATA DIR.
ADC
PORTA REG. PORTA
INTERNAL
OSCILLATOR
STACK WATCHDOG
POINTER
MCU CONTROL
SRAM
REGISTER
GENERAL
COUNTERS
PURPOSE
REGISTERS
X
INTERRUPT
Y
Z
ALU
STATUS PROGRAMMING
REGISTER
SPI
DATA DIR. DATA REGISTER DATA DIR.
REG. PORTE PORTB REG. PORTB
PORTB DRIVER/BUFFERS
PB0 - PB7
PC0 - PC7
PORTC DRIVERS
DATA REGISTER
PORTC
8-BIT DATA BUS
OSCILLATOR
OSCILLATOR
TIMER
TIMING AND
CONTROL
TIMER/
UNIT
EEPROM
LOGIC
UART
DATA REGISTER DATA DIR.
PORTD REG. PORTD
PORTD DRIVER/BUFFERS
PD0 - PD7
XTAL1
XTAL1
TOSC2
TOSC1
RESET
ALE
WR
RD
PEN
VCC
GND
0945G–09/01