Xilinx KCU116 User Manual page 39

Table 3-8 lists the GTY Bank 226 interface connections between FPGA U1 and the four zSFP
connectors J1, J3, J4 and J6.
Table 3‐8: KCU116 FPGA U1 GTY Bank 226 Connections
FPGA
GTY
(U1) FPGA (U1) Pin Name
Bank
Pin
N5 MGTYTXP0_226
N4 MGTYTXN0_226
M2 MGTYRXP0_226
M1 MGTYRXN0_226
L5 MGTYTXP1_226
L4 MGTYTXN1_226
K2 MGTYRXP1_226
K1 MGTYRXN1_226
J5 MGTYTXP2_226
GTY
J4 MGTYTXN2_226
Bank
H2 MGTYRXP2_226
226
H1 MGTYRXN2_226
G5 MGTYTXP3_226
G4 MGTYTXN3_226
F2 MGTYRXP3_226
F1 MGTYRXN3_226
P7 MGTREFCLK0P_226
P6 MGTREFCLK0N_226
M7 MGTREFCLK1P_226
M6 MGTREFCLK1N_226
Notes:
1. Series capacitor AC coupled.
2. MGT connections I/O standard not applicable.
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net Name
SFP0_TX_P
SFP0_TX_N
SFP0_RX_P
SFP0_RX_N
SFP1_TX_P
SFP1_TX_N
SFP1_RX_P
SFP1_RX_N
SFP2_TX_P
SFP2_TX_N
SFP2_RX_P
SFP2_RX_N
SFP3_TX_P
SFP3_TX_N
SFP3_RX_P
SFP3_RX_N
SFP_SI5328_OUT_C_P
SFP_SI5328_OUT_C_N
USER_MGT_SI570_CLOCK_C_P
USER_MGT_SI570_CLOCK_C_N
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Chapter 3: Board Component Descriptions
Connected Connected
Pin Pin Name
18 TD_P
19 TD_N
13 RD_P
12 RD_N
18 TD_P
19 TD_N
13 RD_P
12 RD_N
18 TD_P
19 TD_N
13 RD_P
12 RD_N
18 TD_P
19 TD_N
13 RD_P
12 RD_N
(1)
28 CKOUT1_P
(1)
29 CKOUT1_N
(1)
4
(1)
5 OUT_B
Send Feedback
Connected
Device
SFP0 J1
SFP1 J3
SFP2 J4
SFP3 J6
SI5328B
U20
OUT
SI570 U56
39