Xilinx KCU116 User Manual page 69

Table 3-22 through
FMC connector section pairs.
Table 3‐22: J5 HPC FMC Section A/B Connections to FPGA U1
J5 Pin Schematic Net Name
A2 FMC_HPC0_DP1_M2C_P
A3 FMC_HPC0_DP1_M2C_N
A6 FMC_HPC0_DP2_M2C_P
A7 FMC_HPC0_DP2_M2C_N
A10 FMC_HPC0_DP3_M2C_P
A11 FMC_HPC0_DP3_M2C_N
A14 NC
A15 NC
A18 NC
A19 NC
A22 FMC_HPC0_DP1_C2M_P
A23 FMC_HPC0_DP1_C2M_N
A26 FMC_HPC0_DP2_C2M_P
A27 FMC_HPC0_DP2_C2M_N
A30 FMC_HPC0_DP3_C2M_P
A31 FMC_HPC0_DP3_C2M_N
A34 NC
A35 NC
A38 NC
A39 NC
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Table 3-26 show the FMC HPC0 J5 to XCKU5P FPGA U1 connections in
I/O XCKU5P
Standard (U1) Pin
C4
C3
B2
B1
A4
A3
E5
E4
D7
D6
B7
B6
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Chapter 3: Board Component Descriptions
J5
Schematic Net Name
Pin
B1 NC
B4 NC
B5 NC
B8 NC
B9 NC
B12 NC
B13 NC
B16 NC
B17 NC
B20 FMC_HPC0_GBTCLK1_M2C_P
B21 FMC_HPC0_GBTCLK1_M2C_N
B24 NC
B25 NC
B28 NC
B29 NC
B32 NC
B33 NC
B36 NC
B37 NC
B40 NC
I/O XCKU5P
Standard (U1) Pin
LVDS H7
LVDS H6
69
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