Xilinx KCU116 User Manual page 37

Table 3-7 lists the GTY Banks 224 and 225 interface connections between FPGA U1 and
8-lane PCIe connector P1.
Table 3‐7: KCU116 FPGA U1 GTY Banks 224 and 225 Connections to PCIe Connector P1
Transceiver FPGA
(U1) Pin FPGA (U1) Pin Name
Bank
AFY
AF6
AF2
AF1
AE9
AE8
AE4
AE3
AD7
AD6
GTY Bank
224
AD2
AD1
AC5
AC4
AB2
AB1
ABY
AB6
Y7
Y6
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net
MGTYTXP0_224
MGTYTXN0_224 PCIE_TX7_N
MGTYRXP0_224
MGTYRXN0_224
MGTYTXP1_224
MGTYTXN1_224 PCIE_TX6_N
MGTYRXP1_224
MGTYRXN1_224
MGTYTXP2_224
MGTYTXN2_224 PCIE_TX5_N
MGTYRXP2_224
MGTYRXN2_224
MGTYTXP3_224
MGTYTXN3_224 PCIE_TX4_N
MGTYRXP3_224
MGTYRXN3_224
MGTREFCLK0P_224
MGTREFCLK0N_224
MGTREFCLK1P_224
MGTREFCLK1N_224
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Chapter 3: Board Component Descriptions
Connected
Name Pin
(1)
PCIE_TX7_P A47
(1)
A48
PCIE_RX7_P B45
PCIE_RX7_N B46
(1)
PCIE_TX6_P A43
(1)
A44
PCIE_RX6_P B41
PCIE_RX6_N B42
(1)
PCIE_TX5_P A39
(1)
A40
PCIE_RX5_P B37
PCIE_RX5_N B38
(1)
PCIE_TX4_P A35
(1)
A36
PCIE_RX4_P B33
PCIE_RX4_N B34
NC NA
NC NA
NC NA
NC NA
Connected Connected
Pin Name Device
PERp7
PERn7
PETp7
PETn7
PERp6
PERn6
PETp6
PETn6
PERp5
PERn5
PCIe Edge
Connector P1
PETp5
PETn5
PERp4
PERn4
PETp4
PETn4
NA
NA
NA
NA
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