Xilinx KCU116 User Manual page 21

Table 3‐2: DDR4 Memory Connections to the FPGA (Cont'd)
FPGA (U1) Schematic Net
Pin Name
H18 DDR4_DM2
G15 DDR4_DM3
D25 DDR4_A0
D23 DDR4_A1
D26 DDR4_A2
D24 DDR4_A3
E26 DDR4_A4
C26 DDR4_A5
G22 DDR4_A6
B25 DDR4_A7
F22 DDR4_A8
C24 DDR4_A9
E25 DDR4_A10
F23 DDR4_A11
E23 DDR4_A12
B26 DDR4_A13
H26 DDR4_A14_WE_B
F25 DDR4_A15_CAS_B
F24 DDR4_A16_RAS_B
H22 DDR4_BA0
H21 DDR4_BA1
G26 DDR4_BG0
J26 DDR4_ACT_B
Pulled LOW DDR4_TEN
L24 DDR4_ALERT_B
J25 DDR4_PAR
H24 DDR4_ODT
H23 DDR4_CS_B
M24 DDR4_CKE
L25 DDR4_RESET_B
G24 DDR4_CK_T
G25 DDR4_CK_C
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
I/O Standard
Pin #
POD12_DCI E7
POD12_DCI
SSTL12 P3
SSTL12 P7
SSTL12 R3
SSTL12 N7
SSTL12 N3
SSTL12 P8
SSTL12 P2
SSTL12 R8
SSTL12 R2
SSTL12 R7
SSTL12 M3
SSTL12 T2
SSTL12 M7
SSTL12 T8
SSTL12
SSTL12 M8
SSTL12
SSTL12 N2
SSTL12 N8
SSTL12 M2
SSTL12
SSTL12 N9
SSTL12 P9
SSTL12 T3
SSTL12 K3
SSTL12
SSTL12 K2
LVCMOS12 P1
DIFF_SSTL12_DCI K7
DIFF_SSTL12_DCI K8
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Chapter 3: Board Component Descriptions
Component Memory
Pin Name
DML_B/DBIL_B
E2 DMU_B/DBIU_B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_B
A13
L2 WE_B/A14
CAS_B/A15
L8 RAS_B/A16
BA0
BA1
BG0
L3 ACT_B
TEN
ALERT_B
PAR
ODT
L7 CS_B
CKE
RESET_B
CK_T
CK_C
Send Feedback
Ref. Des.
U153
U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
U150, U153
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