Xilinx KCU116 User Manual page 40

Table 3-9 lists the GTY Bank 227 interface connections between FPGA U1 and FMC HPC0
connector J5
Table 3‐9: KCU116 FPGA U1 GTY Bank 227 Connections
FPGA
GTY FPGA (U1) Pin
(U1)
Bank Name
Pin
F7 MGTYTXP0_227
F6 MGTYTXN0_227
D2 MGTYRXP0_227
D1 MGTYRXN0_227
E5 MGTYTXP1_227
E4 MGTYTXN1_227
C4 MGTYRXP1_227
C3 MGTYRXN1_227
D7 MGTYTXP2_227
GTY
D6 MGTYTXN2_227
Bank
B2 MGTYRXP2_227
227
B1 MGTYRXN2_227
B7 MGTYTXP3_227
B6 MGTYTXN3_227
A4 MGTYRXP3_227
A3 MGTYRXN3_227
K7 MGTREFCLK0P_227
K6 MGTREFCLK0N_227
H7 MGTREFCLK1P_227
H6 MGTREFCLK1N_227
Notes:
1. Series capacitor AC coupled.
2. MGT connections I/O standard not applicable.
For additional information on GTY transceivers, see UltraScale Architecture GTY Transceivers
User Guide (UG578)
Product Guide (PG182)
functionality, see UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP
Product Guide for Vivado Design Suite (PG156)
the PCI Express standard, see
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net Name
FMC_HPC_DP0_C2M_P
FMC_HPC_DP0_C2M_N
FMC_HPC_DP0_M2C_P
FMC_HPC_DP0_M2C_N
FMC_HPC_DP1_C2M_P
FMC_HPC_DP1_C2M_N
FMC_HPC_DP1_M2C_P
FMC_HPC_DP1_M2C_N
FMC_HPC_DP2_C2M_P
FMC_HPC_DP2_C2M_N
FMC_HPC_DP2_M2C_P
FMC_HPC_DP2_M2C_N
FMC_HPC_DP3_C2M_P
FMC_HPC_DP3_C2M_N
FMC_HPC_DP3_M2C_P
FMC_HPC_DP3_M2C_N
FMC_HPC_GBTCLK0_M2C_C_P
FMC_HPC_GBTCLK0_M2C_C_N
FMC_HPC_GBTCLK1_M2C_C_P
FMC_HPC_GBTCLK1_M2C_C_N
[Ref 7]. Also see UltraScale FPGAs Transceivers Wizard LogiCORE IP
[Ref 8]. For additional information about UltraScale PCIe
[Ref 28].
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected Connected Pin
Pin
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
A22 DP1_C2M_P
A23 DP1_C2M_N
A2 DP1_M2C_P
A3 DP1_M2C_N
A26 DP2_C2M_P
A27 DP2_C2M_N
A6 DP2_M2C_P
A7 DP2_M2C_N
A30 DP3_C2M_P
A31 DP3_C2M_N
A10 DP3_M2C_P
A11 DP3_M2C_N
(1)
D4 GBTCLK0_M2C_P
(1)
D5 GBTCLK0_M2C_N
(1)
B20 GBTCLK1_M2C_P
(1)
B21 GBTCLK1_M2C_N
[Ref 18]. For additional information about
Connected
Name Device
FMC
HPC0 J5
40
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