Fpga Configuration - Xilinx KCU116 User Manual

Do NOT plug a PC ATX power supply 6-pin connector into J52 on the KCU116 evaluation
CAUTION!
board. The ATX 6-pin connector has a different pin out than J52. Connecting an ATX 6-pin connector
into J52 damages the KCU116 evaluation board and voids the board warranty.
8. Slide the KCU116 board power switch SW1 to the ON position. The PC can now be
powered on.

FPGA Configuration

The KCU116 board supports two of the five UltraScale
• Quad SPI flash memory
• JTAG using:
USB JTAG configuration port (Digilent module U21)
°
Platform cable header J8
°
Each configuration interface corresponds to one or more configuration modes and bus
widths, as listed in
1, respectively. The FPGA mode pin M2 is wired to SW21 pin 6 (switch position 6), which has
the default setting OPEN, enabling the M2 net to be pulled down to logic 0 (e.g., the FPGA
default mode setting M[2:0] = 001), selecting the Quad SPI configuration mode.
Table 2‐4: Configuration Modes
Configuration Mode
Master SPI
JTAG
For complete details on configuring the FPGA, see UltraScale Architecture Configuration
User Guide (UG570)
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Table 2-4. The FPGA mode pins M1 and M0 are hard wired to logic 0 and
M[2:0]
001
101
[Ref 3].
www.xilinx.com
Chapter 2: Board Setup and Configuration
™
FPGA configuration modes:
Bus Width CCLK Direction
x1, x2, x4 FPGA output
x1 Not applicable
15
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