Xilinx KCU116 User Manual page 70

Table 3‐23: J5 HPC FMC Section C/D Connections to FPGA U1
J5
Schematic Net Name
Pin
C2 FMC_HPC0_DP0_C2M_P
C3 FMC_HPC0_DP0_C2M_N
C6 FMC_HPC0_DP0_M2C_P
C7 FMC_HPC0_DP0_M2C_N
C10 FMC_HPC0_LA06_P
C11 FMC_HPC0_LA06_N
C14 FMC_HPC0_LA10_P
C15 FMC_HPC0_LA10_N
C18 FMC_HPC0_LA14_P
C19 FMC_HPC0_LA14_N
C22 FMC_HPC0_LA18_CC_P
C23 FMC_HPC0_LA18_CC_N
C26 NC
C27 NC
C30 FMC_HPC0_IIC_SCL
C31 FMC_HPC0_IIC_SDA
C34 GA0 = 0 = GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
U1
I/O J5
FPGA
Standard Pin
Pin
F7 D1
F6 D4
D2 D5
D1 D8
LVDS Y20 D9
LVDS Y21 D11
LVDS AF18 D12
LVDS AF19 D14
LVDS AE22 D15
LVDS AF22 D17
LVDS AA22 D18
LVDS AB22 D20
D21
D23
D24
D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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Chapter 3: Board Component Descriptions
Schematic Net Name
VADJ_1V8_PGOOD(3)
FMC_HPC0_GBTCLK0_M2C_P
FMC_HPC0_GBTCLK0_M2C_N
FMC_HPC0_LA01_CC_P
FMC_HPC0_LA01_CC_N
FMC_HPC0_LA05_P
FMC_HPC0_LA05_N
FMC_HPC0_LA09_P
FMC_HPC0_LA09_N
FMC_HPC0_LA13_P
FMC_HPC0_LA13_N
FMC_HPC0_LA17_CC_P
FMC_HPC0_LA17_CC_N
NC
NC
NC
NC
FMC_HPC0_TCK_BUF
FPGA_TDO_FMC_TDI_BUF
FMC_HPC0_TDO
UTIL_3V3
FMC_HPC0_TMS_BUF
NC
GA1 = 0 = GND
UTIL_3V3
UTIL_3V3
UTIL_3V3
I/O U1 FPGA
Standard Pin
K7
K6
LVDS AC19
LVDS AD19
LVDS AA19
LVDS AB19
LVDS AC18
LVDS AD18
LVDS AD23
LVDS AE23
LVDS AD21
LVDS AE21
NA
NA
NA
NA
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