Xilinx KCU116 User Manual page 72

Table 3‐25: J5 HPC FMC Section G/H Connections to FPGA U1
J5
Schematic Net Name
Pin
G2 NC
G3 NC
G6 FMC_HPC0_LA00_CC_P
G7 FMC_HPC0_LA00_CC_N
G9 FMC_HPC0_LA03_P
G10 FMC_HPC0_LA03_N
G12 FMC_HPC0_LA08_P
G13 FMC_HPC0_LA08_N
G15 FMC_HPC0_LA12_P
G16 FMC_HPC0_LA12_N
G18 FMC_HPC0_LA16_P
G19 FMC_HPC0_LA16_N
G21 FMC_HPC0_LA20_P
G22 FMC_HPC0_LA20_N
G24 FMC_HPC0_LA22_P
G25 FMC_HPC0_LA22_N
G27 NC
G28 NC
G30 NC
G31 NC
G33 NC
G34 NC
G36 NC
G37 NC
G39 VADJ _FMC_BUS
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
U1
I/O J5
FPGA
Standard Pin
Pin
NA NA H1
NA NA H2
LVDS AD20 H4
LVDS AE20 H5
LVDS AB17 H7
LVDS AC17 H8
LVDS AE17 H10
LVDS AF17 H11
LVDS AC22 H13
LVDS AC23 H14
LVDS AD24 H16
LVDS AD25 H17
LVDS AF24 H19
LVDS AF25 H20
LVDS AE25 H22
LVDS AE26 H23
NA NA H25
NA NA H26
NA NA H28
NA NA H29
NA NA H31
NA NA H32
NA NA H34
NA NA H35
H37
H38
H40
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Chapter 3: Board Component Descriptions
Schematic Net Name
FMC_HPC0_VREF_A_M2C
FMC_HPC0_PRSNT_M2C_B
FMC_HPC0_CLK0_M2C_P
FMC_HPC0_CLK0_M2C_N
FMC_HPC0_LA02_P
FMC_HPC0_LA02_N
FMC_HPC0_LA04_P
FMC_HPC0_LA04_N
FMC_HPC0_LA07_P
FMC_HPC0_LA07_N
FMC_HPC0_LA11_P
FMC_HPC0_LA11_N
FMC_HPC0_LA15_P
FMC_HPC0_LA15_N
FMC_HPC0_LA19_P
FMC_HPC0_LA19_N
FMC_HPC0_LA21_P
FMC_HPC0_LA21_N
NC
NC
NC
NC
NC
NC
NC
NC
VADJ _FMC_BUS
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U1
I/O
FPGA
Standard
Pin
NA (3)
LVCMOS33
LVDS AB21
LVDS AB22
LVDS Y17
LVDS AA17
LVDS AA20
LVDS AB20
LVDS AD16
LVDS AE16
LVDS Y18
LVDS AA18
LVDS AB24
LVDS AC24
LVDS AC26
LVDS AD26
LVDS AB25
LVDS AB26
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
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