Xilinx KCU116 User Manual page 53

Table 3-16 lists the connections between the codec and the XCKU5P FPGA U1.
Table 3‐16: HDMI Codec U52 to XCKU5P FPGA U1 Connections
FPGA (U1) Pin
V21
V22
T22
T23
W19
W20
Y22
Y23
Y25
Y26
AA24
AA25
W25
W26
V23
W23
V24
W24
U20
T20
P20
U21
V19
U19
R26
Notes: All HDMI nets in this table, except HDMI_INT, are series resistor coupled.
All HDMI nets in this table except HDMI_INT are series resistor coupled.
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net
I/O Standard
Name
HDMI_D0 LVCMOS18
HDMI_D1 LVCMOS18
HDMI_D2 LVCMOS18
HDMI_D3 LVCMOS18
HDMI_D4 LVCMOS18
HDMI_D5 LVCMOS18
HDMI_D6 LVCMOS18
HDMI_D7 LVCMOS18
HDMI_D8 LVCMOS18
HDMI_D9 LVCMOS18
HDMI_D10 LVCMOS18
HDMI_D11 LVCMOS18
HDMI_D12 LVCMOS18
HDMI_D13 LVCMOS18
HDMI_D14 LVCMOS18
HDMI_D15 LVCMOS18
HDMI_D16 LVCMOS18
HDMI_D17 LVCMOS18
HDMI_DE LVCMOS18
HDMI_SPDIF LVCMOS18
HDMI_CLK LVCMOS18
HDMI_VSYNC LVCMOS18
HDMI_HSYNC LVCMOS18
HDMI_SPDIF_OUT LVCMOS18
HDMI_INT LVCMOS18
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Chapter 3: Board Component Descriptions
ADV7511 U52
Pin Number
88
87
86
85
84
83
82
81
80
78
74
73
72
71
70
69
68
67
97
10
79
2
98
46
45
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Name
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
DE
SPDIF
CLK
VSYNC
HSYNC
SPDIF_OUT
INT
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