Xilinx KCU116 User Manual page 43

Table 3‐10: KCU116 FPGA U1 to zSFP0‐zSFP3 Module Connections (Cont'd)
FPGA (U1) Pin
K2
K1
L5
L4
AA14
H2
H1
J5
J4
AA15
F2
F1
G5
G4
Y15
The SFP0_TX_DISABLE/SFP1_TX_DISABLE I/O standard LVCMOS33 and the GTY TX/RX
Note:
connections I/O standard are not applicable.
Table 3-11 lists the zSFP+ module control and status connections.
Table 3‐11: zSFP0‐ zSFP3 Module Control and Status Connections
zSFP Control/
Status Signal
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RS0
SFP_RS1
SFP_LOS
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net
Name
SFP1_RX_P
SFP1_RX_N
SFP1_TX_P
SFP1_TX_N
SFP1_TX_DISABLE_B
SFP2_RX_P
SFP2_RX_N
SFP2_TX_P
SFP2_TX_N
SFP2_TX_DISABLE_B
SFP3_RX_P
SFP3_RX_N
SFP3_TX_P
SFP3_TX_N
SFP3_TX_DISABLE_B
Board Connection
Test Point J57
Jumper J16
Test Point J64
PU R25/ PD R30
PU R227/ PD R142
Test Point J68
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Chapter 3: Board Component Descriptions
Pin Number Pin Name
13
12
18
19
3 TX_DISABLE
13
12
18
19
3 TX_DISABLE
13
12
18
19
3 TX_DISABLE
High = Fault
Low = Normal operation
Off = SFP Disabled
On = SFP Enabled
High = Module not present
Low = Module present
PU R25 = Full RX bandwidth
PD R30 = Reduced RX bandwidth
PU R227 = Full RX bandwidth
PD R142 = Reduced RX bandwidth
High = Loss of receiver signal
Low = Normal operation
SFP/SFP+ Module
RD_P
RD_N
TD_P zSFP1 J3
TD_N
RD_P
RD_N
TD_P zSFP2 J4
TD_N
RD_P
RD_N
TD_P zSFP3 J6
TD_N
SFP Module
zSFP0 J1
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