Xilinx KCU116 User Manual page 47

The Ethernet connections from XCKU5P FPGA U1 to the DP83867ISRGZ PHY device (U12)
are listed in Table
Table 3‐12: Ethernet Connections, XCKU5P MPSoC to the PHY Device
FPGA (U1)
Pin
P25
U25
R25
N24
P24
U26
V26
T24
U24
AA23
T25
P26
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
3-12.
Schematic Net Name
PHY1_MDIO
PHY1_MDC
PHY1_PDWN_B_I_INT_B_O
PHY1_SGMII_IN_P
PHY1_SGMII_IN_N
PHY1_SGMII_OUT_P
PHY1_SGMII_OUT_N
PHY1_SGMII_CLK_P
PHY1_SGMII_CLK_N
PHY1_RESET_B
PHY1_CLKOUT
PHY1_GPIO_0
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Chapter 3: Board Component Descriptions
DP83867 PHY U12
Pin Name
17 MDIO
16 MDC
44 INT_PWDN
27 TX_D1_SGMII_SIP
28 TX_D0_SGMII_SIN
35 RX_D2_SGMII_SOP
36 RX_D3_SGMII_SON
33 RX_D0_SGMII_COP
34 RX_D1_SGMII_CON
43 RESET_B
18 CLK_OUT
39 GPIO_2
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