Comtech EF Data SLM-3650 Installation And Operation Manual page 11

SLM-3650 Satellite Modem Revision 3
Preface MN/SLM3650.IOM
Figure 3-29. IDR/IBS G.703 Master/Master Clocking Diagram............................................................................3-91
Figure 3-30. IDR/IBS G.703 Master/Slave Clocking Diagram ..............................................................................3-92
Figure 3-31. D&I G.703 Master/Master Clocking Diagram...................................................................................3-93
Figure 3-32. Clock Slip ..........................................................................................................................................3-95
Figure 3-33. Doppler Shift......................................................................................................................................3-96
Figure 4-1. M&C Block Diagram.............................................................................................................................4-2
Figure 4-2. Modulator Block Diagram .....................................................................................................................4-8
Figure 4-3. Demodulator Block Diagram ...............................................................................................................4-14
Figure 4-4. Interface Block Diagram......................................................................................................................4-20
Figure 5-1. Fault Isolation Test Setup ......................................................................................................................5-2
Figure 5-2. Typical Output Spectrum (with Noise) ..................................................................................................5-5
Figure 5-3. Typical Output Spectrum (without Noise) .............................................................................................5-5
Figure 5-4. Typical Eye Constellations ....................................................................................................................5-7
Figure A-1. D&I with Asynchronous Overhead Block Diagram ..........................................................................A-10
Figure A-2. D&I with Asynchronous Overhead Data Flow ..................................................................................A-11
Figure A-3. E1 Framing Formats...........................................................................................................................A-16
Figure A-4. T1 Framing Formats...........................................................................................................................A-17
Figure A-5. ASYNC/AUPC Block Diagram .........................................................................................................A-20
Figure A-6. Remote ASYNC Connection Diagram for Y Cable...........................................................................A-29
Figure A-7. Remote ASYNC Connection Diagram for Breakout Panel................................................................A-30
Figure A-8. Sequential Decoder Block Diagram...................................................................................................A-42
Figure A-9. Viterbi Decoder Block Diagram ........................................................................................................A-44
Figure A-10. IDR Interface Block Diagram ..........................................................................................................A-49
Figure A-11. IBS Interface Block Diagram...........................................................................................................A-53
Figure A-12. Transmit Section of the Asymmetrical Loop Timing Block Diagram .............................................A-57
Figure A-13. Receive Section of the Asymmetrical Loop Timing Block Diagram...............................................A-58
Figure A-14. Reed-Solomon PCB ........................................................................................................................A-61
Figure A-15. Reed-Solomon Codec Block Diagram .............................................................................................A-62
Figure A-16. Reed-Solomon Encoder Section Block Diagram .............................................................................A-63
Figure A-17. Reed-Solomon Code Page Format ...................................................................................................A-65
Figure A-18. Reed-Solomon Decoder Section Block Diagram .............................................................................A-66
Figure A-19. Reed-Solomon Codec Installation....................................................................................................A-69
Figure A-20. Overhead Interface PCB Installation................................................................................................A-70
Figure A-21. Main Board Field-Changeable Chips ...............................................................................................A-74
Figure A-22. Overhead Board Field-Changeable Chips........................................................................................A-75
Figure A-23. 8-Channel Multiplexer PCB.............................................................................................................A-76
Figure A-24. 8-Channel Multiplexer Installation ..................................................................................................A-77
Figure A-25. Performance with Noise, Viterbi Decoder and Reed-Solomon (Optional) .....................................A-78
Figure A-26. Overhead Interface PCB Installation................................................................................................A-82
Figure A-27. Main Board Field-Changeable Chips ...............................................................................................A-83
Figure A-28. Overhead Board Field-Changeable Chips........................................................................................A-84
Figure A-29. 8-Channel Multiplexer PCB.............................................................................................................A-85
Figure A-30. Flex Mux..........................................................................................................................................A-90
Figure A-31. Viterbi Decoding..............................................................................................................................A-99
Figure A-32. Sequential Decoding 64 kbps ........................................................................................................A-100
Figure A-33. Sequential Decoding 1024 kbps.....................................................................................................A-101
Figure A-34. Sequential Decoding 2048 kbps.....................................................................................................A-102
Figure A-35. Sequential with cancatenated R-S Outer Code ..............................................................................A-104
Figure A-36. 8-PSK/TCM Rate 2/3 with and without concatenated R-S Outer Code.........................................A-105
Figure A-38. Comtech EF Data Turbo Product Codec Rate 3/4 QPSK/OQPSK, and 8-PSK .............................A-106
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