Jtag; Signal Descriptions; Figure 20. Jtag Topology; Table 25. Generic Routing Requirements - Intel Quark SE Series Platform Manual

10.0

JTAG

This section provides JTAG related information.
10.1

Signal Descriptions

Figure 20. JTAG Topology

Table 25. Generic Routing Requirements

TDO/TDI/TMS/TCK
Transmission Line Segment
Routing Layer
(Microstrip/Stripline/Dual
Stripline)
Characteristic Impedance (SE)
Trace Width (w)
Trace Spacing(S): Both
between JTAG signals and to
other signals
Trace Length
Total Trace Length
Max unterminated stub
length
Length mismatch between
DATA and TCK
Reference
Termination
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
44
TDO
Intel®
Quark SE
SoC
VREF_DEBUG
Lterm1
Main Routing
50Ω +/- 10%
Meet impedance
L1 + Lterm(1/2)
<5500 mils
<5500 mils
<1100 mil
<250 mil
VSS referencing
R1 = 51 Ω +/- 5%; R2 = 51 Ω +/- 5%
VREF_DEBUG
R2
L1 Lterm2
R1
TDI/TMS/TCK
L1
JTAG
Termination
Route for TDO
TL1 TLterm2
MS/SL MS/SL
50Ω +/- 10%
Meet impedance
3W 3W
<250 mils
Document Number: 334715-004EN
JTAG
Debug
connector
Termination
Route for
TDI/TMS/TCK
TLterm1
MS/SL
50Ω +/- 10%
Meet
impedance
3W
<1100 mil
June 2017