Spi; Signal Descriptions; Figure 15. Spi Point-To-Point Single Flash Topology; Table 14. Spi Signals - Intel Quark SE Series Platform Manual

7.0

SPI

The Serial I/O implements two SPI controllers that support master mode and one
SPI controller that supports slave mode. Refer to the Intel® Quark™ SE
Microcontroller C1000 Datasheet for additional SPI compatibility requirements and
features. Support for SPI Flash devices is a key platform requirement and is needed
for all SoC designs.

Table 14. SPI Signals

Signal Name
SPI_M_x_SCK
SPI_M_x_CS_B[3:0]
SPI_M_x_MOSI
SPI_M_x_MISO
The Intel® Quark™ SE microcontroller C1000 includes the following:

Two SPI master interfaces with support for SPI clock frequencies up to 16 MHz
 One SPI slave interface with support for SPI clock frequencies up to 3.2 MHz
 Support for 4-bit up to 32-bit frame size
 Up to four Slave Select pins per master interface
 FIFO mode support (16B TX and RX FIFOs)
 Support for HW DMA with configurable FIFO thresholds
7.1

Signal Descriptions

Figure 15. SPI Point-to-Point Single Flash Topology

ATP SoC

Table 15. SPI Single Flash Platform Routing Guidelines

MOSI/MISO/SPI_IO/CLK/CS
Transmission Line Segment
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
34
Direction/ Type
Output
Output
Output
Input
TL0
Single Load
MOSI/MISO/SPI_IO/CLK/CS
SPI Serial Clock
SPI Chip Select
SPI Master Output Slave Input
SPI Master Input Slave Output
TL1
SPI Single Flash
SoC Breakout Main Routing
TL0
Document Number: 334715-004EN
Description
Rs TL2
FLASH
Device
Device Breakout
TL1 TL2
June 2017
SPI