Figure 16. Spi Point-To-Point Dual Flash Topology - Intel Quark SE Series Platform Manual

SPI
MOSI/MISO/SPI_IO/CLK/CS
Routing Layer
(Microstrip/Stripline/Dual
Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S1): Between
SPI signals
Trace Spacing (S2): Between
SPI signals and other signals
Trace Spacing(S3): Between
SPI_CLK to other signals
Trace Length
Length mismatch between
SPI_CLK and SPI_CS
Length mismatch between
SPI_CLK and DATA
(SPI_IO/MOSI/MISO)
Trace Total Length
Number of vias allowed
Via stub length
Rs
Reference
W

Figure 16. SPI Point-to-Point Dual Flash Topology

ATP SOC
June 2017
Document Number: 334715-004EN
SoC Breakout
3.5 mils minimum
<250 mils
<250 mils
1500 mils < Total Length < 10000 mils
4
< 80 mils
33Ω
VSS referencing
W is the trace width
TL0
Dual Load
MOSI/MISO/SPI_IO/CLK
SPI Single Flash
Main Routing
MS/SL MS/SL
50Ω +/- 10% 50Ω +/- 10%
impedance
4 mils
5 mils
5 mils
1500 mils <
<100 mils TL0+TL1+TL2
< 10000 mils
TL2
TL1
TL2
Intel® Quark™ SE Microcontroller C1000
Device Breakout
MS/SL
50Ω +/- 10%
Meet
Meet impedance
3W 2W
3W
2W
3W 2W
<500 mils
Rs TL3 FLASH
Device 0
Rs TL3 FLASH
Device 1
Platform Design Guide
35