Features; Table 17. Spi_Cs Dual Flash Platform Routing Guidelines - Intel Quark SE Series Platform Manual

SPI

Table 17. SPI_CS Dual Flash Platform Routing Guidelines

SPI_CS
Transmission Line Segment
Routing Layer
(Microstrip/Stripline/Dual
Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S1): Between
SPI signals
Trace Spacing (S2): Between
SPI signals and other signals
Trace Spacing(S3): Between
SPI_CLK to other signals
Trace Length
Length mismatch between
SPI_CLK and SPI_CS
Length mismatch between
SPI_CLK and DATA
(SPI_IO/MOSI/MISO)
Length mismatch between
branches of same net
Trace Total Length
Number of vias allowed
Via stub length
Rs
Reference
W
7.2

Features

The following is a list of the SPI master features:
 Two SPI master interfaces
 Control of up to four Slave Selects
 Frame formats:



 Transfer modes:
June 2017
Document Number: 334715-004EN
Motorola* SPI
Texas Instruments* SSP
National Semiconductor Microwire*
SPI_CS Dual Flash
SoC Breakout Main Routing
TL0
MS/SL
50Ω +/- 10% 50Ω +/- 10%
3.5 mils minimum
4 mils
5 mils
5 mils
1500 mils <
<100 mils TL0+TL1+TL2
<250 mils
<250 mils
<100 mils
1500 mils < Total Length of Single Flash Device < 8000
mils
4
< 80 mils
33Ω
VSS referencing
W is the trace width
Intel® Quark™ SE Microcontroller C1000
Device Breakout
TL1 TL2
MS/SL MS/SL
50Ω +/- 10%
Meet
Meet impedance
impedance
3W
3W
3W
<500 mils
< 8000 mil
Platform Design Guide
2W
2W
2W
37