Agilent Technologies 16712A Help Manual page 73

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
Importing Netlist and ASCII Files
Default Setup and Hold
If the relationship of the clock signal and valid data is such that the
data is valid for 1 ns before the clock occurs and 3 ns after the clock
occurs, you will want to use the 1.0 setup and 2.5 hold setting.
Clock Position in Valid Data
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