Agilent Technologies 16712A Help Manual page 44

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
The Sampling Tab
Mode field
The Mode field lets you select among Master only, Master/slave, and
Demultiplex. The default is Master only. When you select the others,
another control to set the slave clock appears at the bottom of the
Clock Setup area. It also enables the Pod Clock field under Format.
For more detail on the uses of Master/slave and Demultiplex clocking,
see "Clock Modes (State only)" on page 43.
Advanced Clocking
Advanced clocking allows you to specify clock qualifiers on individual
clock edges instead of the group of clock edges. When you select it, the
individual clock channels are replaced by Master Clock... or Slave
Clock... Selecting these brings up a dialog that lets you combine edges
and qualifiers in more complex Boolean expressions. When you switch
from Advanced Clocking to regular clocking, some of the qualifiers are
erased.
Clock Channel Specifiers
The clock channel specifiers graphically show your clock setup. Edges
are ORed ("+") together, and qualifiers are ANDed (".") to all edges. To
qualify just one of the edges, switch to Advanced Clocking.
All clock channels for the clock setup must be on the pods of the
master card of the module, but the pods do not need to be part of the
state measurement.
See Also "Clock Modes (State only)" on page 43
Clock Modes (State only)
The Pod Clock field under Format appears when a clock mode other
than Master only is selected in Sampling. The Pod Clock field
indicates whether a pod's data lines are to be sampled into memory by
the master clock, slave clock, or both (demultiplex).
The Pod Clock field and the clocking arrangement are only available in
a state analyzer.
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