Agilent Technologies 16712A Logic Analyzer Characteristics - Agilent Technologies 16712A Help Manual

Minimum Master-to-Master Clock Time:* 10.0 ns
Setup/Hold Time:*
Single Clock, Single Edge:
Single Clock, Multiple Edge:
Multiple Clock, Multiple Edge:
* Specified for an input signal VH=-0.9 V, VL=-1.7 V, threshold=-1.3 V,
slew rate=1 V/ns
Agilent Technologies 16712A Logic Analyzer
Characteristics
The characteristics are not specifications, but are included as
additional information.
General information
- Channel Counts:
1-card module
2-card module
- Memory Depth:
16710A
16711A
16712A
Probes
- Input Resistance:
- Parasitic tip capacitance:
- Minimum Voltage Swing:
- Maximum Voltage:
- Threshold Range:
State Analysis
- Maximum State Clock Speed
- Minimum State Clock Pulse Width:
- Minimum Slave-to-Slave Clock Time
- Minimum Master-to-Slave Clock Time
- Minimum Slave-to-Master Clock Time
- State Clocks:
- State Clock Qualifiers:
- State Clock Qualifier Setup/Hold
- Time Tag Resolution:
- Maximum Time Count Between States:
- Maximum State Tag Count:
- Context Store Block Sizes
** Minimum times are given for an input signal
VH=-0.9 V, VL=-1.7 V, threshold=-1.3 V, slew rate=1 V/ns
Timing Analysis
- Maximum Conventional Timing Rate:
Half Channel
Full Channel
- Maximum Transitional Timing Rate:
Full Channel
- Sample Period Accuracy:
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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
0.0/5.0 ns through 5.0/0.0 ns,
adjustable in 500-ps increments
96 data, 6 clock
198 data, 6 clock
Full Channel
8 Ksamples
32 Ksamples
128 Ksamples
100 Kohm, +/- 2%
1.5 pF
500 mV peak-to-peak
+/- 40 V peak, CAT I
+/- 6.0 V, adjustable in 50-mV increments
100 MHz
3.5 ns**
10.0 ns**
0.0 ns**
4.0 ns**
6
4
4.0/0.0 ns, not adjustable
8 ns
34.3 seconds
4.29e9
16/32/64 states
500 MHz
250 MHz
125 MHz
0.01% of sample period
Specifications and Characteristics
Half Channel
16 Ksamples
64 Ksamples
256 Ksamples
Each qualifier can be set to
recognize one of six clock
lines, either high or low.
105