Port State Sense Register - Keysight VXI Bus 75000 C Series User And Programming Manual

Register Descriptions
IPIR (Invert PIR). This bit specifies the logic sense of a peripheral interrupt request.
If bit 4 = 0, a rising-edge (low to high) transition of the PIR line triggers an
interrupt. If bit 4 = 1, a falling-edge (high to low) transition of the PIR line triggers
an interrupt. In either case, no interrupt occurs unless peripheral interrupts are
enabled.
IFLG (Invert FLG). This bit specifies the logic sense of the FLG line.
ICTL (Invert CTL). This bit specifies the logic sense of the CTL line.
ID (Invert DATA). This bit specifies the logic sense of the port data lines.

Port State Sense Register

The Port State Sense Register is a read-only register. This register performs an
active read-back of the state of the port data lines, independent of the state of
the Port Data Register. The ports affected by this register are set by the BB1 and
BB0 bits in the Card Status/Control Register.
D0-D7 correspond to data lines Dn_0 through Dn_7. Bit 7 is the most significant
bit. The values of these bits are not affected by the Port Normalization Register.
A 1 indicates a data line in the TTL High condition.
Keysight E1458A 96-Channel Digital I/O Module User Guide
If bit 5 = 0, then positive-true logic is used: HIGH = BUSY, LOW = READY. If
bit 5 = 1, then negative-true logic is used: LOW = BUSY, HIGH = READY.
If bit 6 = 0, then positive-true logic is used: HIGH = TRUE, LOW = FALSE. If
bit 6 = 1, then negative-true logic is used: LOW = TRUE, HIGH = FALSE.
If bit 7 = 0, then positive-true logic is used: HIGH = TRUE, LOW = FALSE. If
bit 7 = 1, then negative-true logic is used: LOW = TRUE, HIGH = FALSE.
base+2C16, base+2D16, base+2E16, base+2F16
7 6 5
D7 D6 D5
Keysight E1458A Register Information
4 3 2
D4 D3 D2
1 0
D1 D0
135