Port Handshake Register - Keysight VXI Bus 75000 C Series User And Programming Manual

Keysight E1458A Register Information
Bits 0-7 of the Port Data Register correspond to data lines D (0-7) where bit 7 is
the most significant bit.

Port Handshake Register

The Port Handshake Register determines the type of handshake protocol used
for the port data transfers and how the data is transferred from the Keysight
E1458A Digital I/O Module to the mainframe on the VXIbus. The ports affected
by this register are set by the BB1 and BB0 bits in the Card Status/Control
Register.
TM (0,1)(Transfer Mode). These bits control the transfer mode for the port between
the digital I/O module and the VXIbus as shown in Table B-3.
The three transfer modes are used to transfer data between the VXIbus and the
digital I/O module:
Bits 2 and 3. Unused
132
– When the Port Data register is read the following bits are set to 0 on the
Port Transfer Control Register: DRR (bit 0), TI (bit 5), and PI (bit 7).
base+3016, base+3116, base+3216, base+3316
7 6 5
HT2 HT1 HT0
Table B-3. Transfer Mode
Transfer Mode
Flag Driven
Interrupt Driven
Fast Handshake
– Flag Driven – the mainframe polls the Data Register Ready bit (bit 0, Port
Transfer Control Register). When this bit is set, it reads data from the Port
Data Register or writes data to the Port Data Register.
– Interrupt Driven – the peripheral sets bit 1 of the Port Status/Control
Register (via the PIR line) and the digital I/O module interrupts the VXIbus
for data transfer with the mainframe.
– Fast Handshake – the peripheral talks directly with the VXIbus's Data
Acknowledge line to transfer data between the Port Data Registers and the
VXIbus.
4 3 2
EI — —
TM1 (Bit 1) TM0 (Bit 0)
0 0
0 1
1 0
Keysight E1458A 96-Channel Digital I/O Module User Guide
Register Descriptions
1 0
TM1 TM0