Port Control/Status Register - Keysight VXI Bus 75000 C Series User And Programming Manual

Keysight E1458A Register Information

Port Control/Status Register

The Port Control/Status Register is a read/write register that controls and shows
the status of the port control lines (STS, PIR, FLG, RES, I/O and CTL). The ports
affected by this register are set by the BB1 and BB0 bits in the Card
Status/Control Register.
STS. Bit 0 is a read-only bit. Read this bit to find the status of the STS line which
is an input from the peripheral for the port. A 1 shows that the line is BUSY; a 0
shows that the line is READY.
PIR. Bit 1 is a read-only bit. This bit shows the normalized state of the PIR line
which is an input line from the peripheral:
If peripheral interrupts are not enabled, you can use the PIR line as a secondary
status line. Just read bit 1 to monitor the state of the line.
If peripheral interrupts are enabled, you can still monitor the status of the PIR
line by reading bit 1. However, the current status of the PIR line does not indicate
whether a peripheral interrupt has occurred. Port peripheral interrupts are
caused by transitions in the state of the PIR line. Read bit 7 of the Port Transfer
Control Register to determine whether a port peripheral interrupt has occurred.
Bits 2 and 3. Unused
FLG. This is a read-only bit. Read this bit to find the normalized status of the FLG
line. A 1 shows that the line is BUSY; a 0 shows that the line is READY. This bit
shows the logical state (BUSY or READY) of the FLG line, regardless of the logic
sense.
RES. This is a read/write bit. Reading this bit shows the current state of the RES
line which is an output line to the peripheral. A 1 shows that the line is high; a 0
shows that the line is low. Bit 5 is initially set to 0 by a hardware reset of the
interface. This causes the RES line to go low, resetting the peripheral (if the
peripheral implements the reset feature). You can control the logical state of the
RES line by writing to this bit. Set bit 5 equal to 1 to change RES to the high
state. The peripheral will then operate normally. To reset the peripheral, set bit 5
to 0, putting RES in the low state.
130
base+2816, base+2916, base+2A16, base+2B16
7 6 5
CTL I/O RES
– If positive-true logic is in use (bit 4 of the Port Normalization Register is
equal to 0), bit 1 is equal to 0 if the line is low, 1 if the line is high.
– If the PIR line is inverted (bit 4 of the Port Normalization Register is equal
to 1), bit 1 is equal to 0 if the line is high, 1 if the line is low.
4 3 2
FLG — —
Keysight E1458A 96-Channel Digital I/O Module User Guide
Register Descriptions
1 0
PIR STS